PM5395-BI PMC-Sierra Inc, PM5395-BI Datasheet
PM5395-BI
Related parts for PM5395-BI
PM5395-BI Summary of contents
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... CRSU™ 4x2488 Quad Clock Recovery and Synthesis Unit for 2488 Mbit/s Issue 5: December, 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PM5395 Data Sheet Released Released ...
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Legal Information Copyright © 2002 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written ...
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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Revision History Issue Issue Date Details of Change No. 5 December Updated power numbers. 2002 Added reference to Bellcore spec GR253 -CORE 1995 and 2000 release. Note added to QSFI-4 Common Electrical Interface Overview, detailing the QSFI-4 is not IEEE ...
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Table of Contents Legal Information.................................................................................................................2 Copyright .............................................................................................................2 Disclaimer............................................................................................................2 Trademarks .........................................................................................................2 Patents ................................................................................................................2 Contacting PMC-Sierra........................................................................................................3 Revision History...................................................................................................................4 Table of Contents.................................................................................................................5 List of Registers.................................................................................................................10 List of Figures ....................................................................................................................14 List of Tables......................................................................................................................15 1 Definitions ...................................................................................................................16 2 Features ......................................................................................................................18 2.1 General .............................................................................................................18 2.2 SONET ...
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Functional Description ................................................................................................56 10.1 Receive Line Interface 10.2 SONET/SDH Receive Line Interface 10.3 Receive Regenerator and Multiplexor Processor (RRMP) 10.4 Receive In-band Forward Error Correction Decoder (RIFD) 10.4.1 FEC Decoder........................................................................................60 10.4.2 Performance Monitors 10.5 SONET/SDH Bit Error Rate Monitor ...
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States..................................................................................................244 12.4.3 Instructions 13 Operation ..................................................................................................................246 13.1 Initialization Settings 13.1.1 TRSP Register settings: 13.2 System side interface issues 13.2.1 B1 Byte Recalculated 13.2.2 Line side data frequency out of specification 13.3 QSFI-4 Common Electrical Interface Overview 13.3.1 LVDS Receiver ...
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Line side, Channel to Channel Loopback Operation Register 000DH: Diagnostic Loopback and ICO Register 10A1H: TXLI CSU Control Register 12A1H: TXLI CSU Control Register 000FH: Bypass and Loop-across 13.13 Interrupt Service Routine 13.14 Using the Performance Monitoring Features 13.14.1 ...
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet Released 9 ...
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List of Registers Register 0000H: Identity and Global Performance Monitor Update Trigger .....................84 Register 0001H: Master Reset ..........................................................................................86 Register 0002H: Master Interrupt Status RX CH0 ............................................................88 Register 0003H: Master Interrupt Status RX CH1 ............................................................90 Register 0004H: Master Interrupt Status RX ...
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Register 1050H: TRSP Configuration .............................................................................145 Register 1051H: TRSP Register Insertion.......................................................................147 Register 1052H: TRSP Error Insertion ............................................................................149 Register 1053H: TRSP Transmit J0 and Z0....................................................................151 Register 1054H: TRSP Transmit E1 and F1 ...................................................................152 Register 1055H: TRSP Transmit D1D3...........................................................................153 Register 105AH: TRSP Transmit ...
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Register 1106H – 110FH: RXLI Reserved ......................................................................186 Register 1110H: SRLI Clock Configuration .....................................................................186 Register 1120H: RRMP Configuration ............................................................................187 Register 1121H: RRMP Status........................................................................................190 Register 1122H: RRMP Interrupt Enable ........................................................................192 Register 1123H: RRMP Interrupt Status .........................................................................193 Register 1124H: RRMP Receive APS.............................................................................196 Register ...
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Register 118AH: SBER SF BERM Clearing Threshold (LSB) ........................................223 Register 118BH: SBER SF BERM Clearing Threshold (MSB) .......................................223 Register 118CH: SBER SD BERM Accumulation Period (LSB) .....................................224 Register 118DH: SBER SD BERM Accumulation Period (MSB) ....................................224 Register 118EH: SBER SD ...
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List of Figures Figure 1 2.488 Gbit/s Stream Pure SERDES Application ...............................................22 Figure 2 STS-48 (STM-16) SERDES Application ...........................................................23 Figure 3 STS-48 (STM-16) FEC Line Regeneration Equipment (LRE) Application.......................................................................................................24 Figure 4 Normal Operation..............................................................................................25 Figure 5 Loop-back and Bypass Operation Modes.........................................................26 ...
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List of Tables Table 1 Abbreviations Used in this Document ................................................................16 Table 2 CRSU 4x2488 Modes of Operation....................................................................28 Table 3 CRSU 4x2488 Top Left Corner Pin-Out..............................................................30 Table 4 CRSU 4x2488 Bottom Left Corner Pin-Out.........................................................31 Table 5 CRSU 4x2488 Top Right ...
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Definitions The following table defines the abbreviations for the CRSU™ 4x2488. Table 1 Abbreviations Used in this Document AIS Alarm Indication Signal AIS-L Alarm Indication Signal for Line overhead APS Automatic Protection Switching ASSP Application Specific Standard Product ATM ...
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PISO Parallel to Serial Converter PLL Phase-Locked Loop POS Packet Over SONET PPP Point-to-Point Protocol PRBS Pseudo-Random Bit Sequence QSFI-4 Quad Serdes/Framer Electrical Interface RDI-L Line Remote Defect Indication RRMP Receive Regenerator and Multiplexor Processor RDI Remote Defect Indication RIFD ...
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Features 2.1 General Single chip Clock Recovery and Synthesis Unit supporting four SONET/SDH links operating at 2488.32 Mbit/s. Processes four independent bit-serial 2488.32 Mbit/s STS-48 (STM-16) data streams with on- chip clock and data recovery and clock synthesis. Complies ...
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Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for the receive stream. Calculates and inserts B1 in the transmit stream. Accumulates near end errors (B1, B2) and far end errors (M1). Extracts and filters the ...
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Applications DWDM Terminal Multiplexers. ATM and Multi-service Switches, routers, and switch/routers SONET/SDH Add/Drop Multiplexers with data processing capabilities SONET/SDH ATM/POS Test Equipment Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 ...
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References 1. Applicable Recommendations and Standards. The designer is required to read these references during the Design Planning task. See the Device Design Procedure, PMC- 1940424. 2. Telcordia - GR-253-CORE “SONET Transport Systems: Common Generic Criteria”, Issue 3, September ...
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... Application Examples The PM5395 CRSU 4x2488 is applicable to many types of equipment that implement a 2.488 Gbit/s serial interfaces. When the device is configured for pass through mode the CRSU 4x2488 bridges between an optical module and a Protocol Processor. No higher level processing of the data is done after the data is extracted from the serial stream. In this mode, the CRSU 4x2488 may serve as the SERDES for data streams of arbitrary formats provided for optical line-side data rates of 2 ...
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... The PM5395 CRSU 4x2488 is applicable to equipment implementing SONET OC-48 or SDH STM-16 interfaces. Figure 2 shows the CRSU 4x2488 connected to the S/UNI-9953 OC-192 Physical Layer Device. The CRSU 4x2488 also directly connects to the SPECTRA-9953 SONET/SDH Payload Extractor Aligner for channelized OC-192 applications. In addition to bridging between the optical module and the SONET/SDH framer devices, the CRSU 4x2488 optionally performs SONET section and line layer or SDH regenerator and multiplex section performance monitoring ...
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Figure 3 STS-48 (STM-16) FEC Line Regeneration Equipment (LRE) Application Optical Data Link Optical Data Link Optical Data Link Optical Data Link Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ ...
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Block Diagram Figure 4 Normal Operation CRU (4) SD[3:0] SRLI RXD[3:0]+/- RXLI (4) (4) REFCLK[3:0]+/- TXENB[3:0] STLI TXLI (4) TXD[3:0]+/- Tx Line C0[3:0] CSU (4) C1[3:0] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ...
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Figure 5 Loop-back and Bypass Operation Modes CRU (4) SD[3:0] SRLI RXD[3:0]+/- RXLI (4) (4) SDLE REFCLK[3:0]+/- TXENB[3:0] STLI TXLI LPLE_TX (4) & LPLE_RX TXD[3:0]+/- Tx Line C0[3:0] CSU (4) C1[3:0] Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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... Description The PM5395 CRSU 4x2488 Quad Clock Recovery and Synthesis Unit Interface is a monolithic integrated circuit that bridges between the optical module and the SONET/SDH framer devices. It provides clock and data recovery functions in the receive direction and clock synthesis functions in the transmit direction. The interfaces to the optical module are serial 2.488 Gbit/s streams and the interface to SONET/SDH framers is a quad 4-bit version of the Optical Internetworking Forum SFI-4 Specification ...
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Table 2 CRSU 4x2488 Modes of Operation Operational Mode SERDES Mode PMON Mode Regenerator Mode SERDES Mode In SERDES Mode, the CRSU 4x2488 provides clock recovery and synthesis for four independent bit-serial streams. In this mode, the CRSU 4x2488 can ...
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Regenerator Mode The CRSU 4x2488 provides a Regenerator Mode to support dense regenerator applications. In this mode, the CRSU 4x2488 provides an internal connection between channel 0 to channel 1 and from channel 2 to channel 3. The CRSU 4x2488 ...
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Pin Diagram Table 3 CRSU 4x2488 Top Left Corner Pin-Out vss vss vss vss vss avdl_qs A fim vss vss vss vss res B avdl_qs fim vss vss vss vss resk VSS C ...
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Table 4 CRSU 4x2488 Bottom Left Corner Pin-Out V c0[0] c1[0] avdh_cr avdh_cr avdh_cr u_0 u_0 u_0 W vss VSS VSS qavd avdl_0 Y rxd[0]+ vss avdh_cr avdh_cr avdh_cr u_0 u_0 u_0 AA rxd[0]- vss vss vss avdl_0 AB vss ...
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Table 5 CRSU 4x2488 Top Right Corner Pin-Out rxdata3 rxdata3 vss vddi txdata0 txdata0 txdata1 [1]+ [2]+ [1]+ [2]+ [0]+ rxdata3 rxdata3 vddi vddi txdata0 txdata0 txdata1 [1]- [2]- [1]- [2]- [0]- rxclk3- ...
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Table 6 CRSU 4x2488 Bottom Right Corner Pin-Out vddi sd[1] vddi avdh_cr avdl_2 avdh_cr avdl_2 u_2 u_2 vddi sd[2] txenb[2 avdh_cr qavd avdh_cr vss ] u_2 u_2 VSS sd[3] txenb[3 avdh_cr VSS avdh_cr vss ] u_2 u_2 NC vddo txenb[1 ...
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Pin Description 9.1 Serial Line Side Interface Signals (33) Pin Name Type REFCLK[3]+ Differential REFCLK[3]- PECL REFCLK[2]+ Input REFCLK[2]- REFCLK[1]+ REFCLK[1]- REFCLK[0]+ REFCLK[0]- RXD[3]+ Differential RXD[3]- PECL RXD[2]+ Input RXD[2]- RXD[1]+ RXD[1]- RXD[0]+ RXD[0]- TXD[3]+ Differential TXD[3]- CML TXD[2]+ ...
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Clocks and Alarms (12) Pin Name Type RCLK[3] Output RCLK[2] RCLK[1] RCLK[0] Output TCLK[3] TCLK[2] TCLK[1] TCLK[0] Output SALM[3] SALM[2] SALM[1] SALM[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 ...
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System Side Interface Signals (100) Pin Name Type RXDATA0[3]+ Analog RXDATA0[3]- LVDS RXDATA0[2]+ Output RXDATA0[2]- RXDATA0[1]+ RXDATA0[1]- RXDATA0[0]+ RXDATA0[0]- RXCLK0+ Analog RXCLK0- LVDS Output RXDATA1[3]+ Analog RXDATA1[3]- LVDS RXDATA1[2]+ Output RXDATA1[2]- RXDATA1[1]+ RXDATA1[1]- RXDATA1[0]+ RXDATA1[0]- Proprietary and Confidential to ...
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Pin Name Type RXCLK1+ Analog RXCLK1- LVDS Output RXDATA2[3]+ Analog RXDATA2[3]- LVDS RXDATA2[2]+ Output RXDATA2[2]- RXDATA2[1]+ RXDATA2[1]- RXDATA2[0]+ RXDATA2[0]- RXCLK2+ Analog RXCLK2- LVDS Output RXDATA3[3]+ Analog RXDATA3[3]- LVDS RXDATA3[2]+ Output RXDATA3[2]- RXDATA3[1]+ RXDATA3[1]- RXDATA3[0]+ RXDATA3[0]- Proprietary and Confidential to PMC-Sierra, ...
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Pin Name Type RXCLK3+ Analog RXCLK3- LVDS Output TXCLK_SRC0+ Analog TXCLK_SRC0- LVDS Output TXCLK0+ Analog TXCLK0- LVDS Input TXDATA0[3]+ Analog TXDATA0[3]- LVDS TXDATA0[2]+ Input TXDATA0[2]- TXDATA0[1]+ TXDATA0[1]- TXDATA0[0]+ TXDATA0[0]- Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Pin Name Type TXCLK_SRC1+ Analog TXCLK_SRC1- LVDS Output TXCLK1+ Analog TXCLK1- LVDS Input TXDATA1[3]+ Analog TXDATA1[3]- LVDS TXDATA1[2]+ Input TXDATA1[2]- TXDATA1[1]+ TXDATA1[1]- TXDATA1[0]+ TXDATA1[0]- TXCLK_SRC2+ Analog TXCLK_SRC2- LVDS Output Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Pin Name Type TXCLK2+ Analog TXCLK2- LVDS Input TXDATA2[3]+ Analog TXDATA2[3]- LVDS TXDATA2[2]+ Input TXDATA2[2]- TXDATA2[1]+ TXDATA2[1]- TXDATA2[0]+ TXDATA2[0]- TXCLK_SRC3+ Analog TXCLK_SRC3- LVDS Output TXCLK3+ Analog TXCLK3- LVDS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Pin Name Type TXDATA3[3]+ Analog TXDATA3[3]- LVDS TXDATA3[2]+ Input TXDATA3[2]- TXDATA3[1]+ TXDATA3[1]- TXDATA3[0]+ TXDATA3[0]- SYNC_ERR[3] Output SYNC_ERR[2] SYNC_ERR[1] SYNC_ERR[0] PHASE_INIT[3] Input PHASE_INIT[2] PHASE_INIT[1] PHASE_INIT[0] PHASE_ERR[3] Output PHASE_ERR[2] PHASE_ERR[1] PHASE_ERR[0] Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal ...
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Microprocessor Interface Signals (36) Pin Name Type CSB Input RDB Input WRB Input D[15] I/O D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[13] Input A[12] Input A[11] A[10] A[9] A[8] A[7] ...
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Pin Name Type ALE Input INTB OD Output 9.5 JTAG Test Access Port (TAP) Signals (5) Pin Name Type TCK Input TMS Input TDI Input TDO Tri-state Output TRSTB Schmidt TTL Input 9.6 Analog Miscellaneous Signals (32) Pin Name Type ...
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Pin Name Type C0[3] Analog C1[3] Signal C0[2] C1[2] C0[1] C1[1] C0[0] C1[0] NC Output VSS Input LCRUTO[3] Output LCRUTO[2] LCRUTO[1] LCRUTO[0] RES Analog RESK Signal 9.7 Analog Power (120) Pin Name Pin Type QAVD (4) Analog Power AVDH_CRU_0 Analog ...
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Pin Name Pin Type AVDH_CRU_1 Analog (6) Power AVDH_CRU_2 Analog (6) Power AVDH_CRU_3 Analog (6) Power AVDH_TX_0 (3) Analog Power AVDH_TX_1 (3) Analog Power AVDH_TX_2 (3) Analog Power AVDH_TX_3 (3) Analog Power AVDH_CSU_0 Analog (4) Power Proprietary and Confidential to ...
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Pin Name Pin Type AVDH_CSU_1 Analog (4) Power AVDH_CSU_2 Analog (4) Power AVDH_CSU_3 Analog (4) Power AVDH_QSFIM Analog (13) Power AVDL_0 (9) Analog Power AVDL_1 (8) Analog Power Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use ...
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Pin Name Pin Type AVDL_2 (9) Analog Power AVDL_3 (9) Analog Power AVDL_QSFIM Analog (16) Power Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet ...
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Digital Power (56) Pin Name Pin Type VDDO (33) Digital Switching Power Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PIN Function No. ...
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Pin Name Pin PIN Type No. VDDI (23) Digital G30 Core J30 Power L30 N30 R30 T32 AK19 AK18 AL18 AK16 B15 A15 B16 AJ4 AJ5 AH30 AH31 Proprietary and Confidential to PMC-Sierra, Inc., ...
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Ground (186) Pin Name Pin Type VSS (186) Digital Ground Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PIN Function No. The ground ...
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Pin Name Pin Type VSS (continued) Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PIN Function No. AK1 AK2 AK3 AK4 AK5 AL1 AL2 ...
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Pin Name Pin Type VSS (continued) Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PIN Function No. AN22 AP22 AL23 AM23 AN23 AL24 AM24 ...
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Pin Name Pin Type VSS (continued) Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet PIN Function No. AJ34 AH32 AH33 AH34 AF33 AF34 AE33 ...
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Pin Name Pin Type VSS (continued) 9.10 Pad Summary Digital Inputs Interface Serial Line Side Interface OIF SFI-4 Interface Clocks and Alarms Microprocassor JTAG Test Access Port Analog misc 1.8 V Analog Power 3.3 V Analog Power 1.8 V Digital ...
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The CRSU 4x2488 digital outputs and bidirectionals which have 6mA drive capability are: SALM[3:0], TXENB[3:0], SYNC_ERR[3:0], PHASE_ERR[3:0]. The CRSU 4x2488 digital outputs and bidirectionals which have 9mA drive capability are: RCLK[3:0], TCLK[3:0], TDO and INTB. 3. The CRSU 4x2488 ...
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Functional Description This section provides detail on the functional description of the CRSU 4x2488. Table 7 outlines the blocks that are used in the main modes of operation and the optional functions and their corresponding blocks. Table 7 Functional ...
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... Figure 6 Typical STS-48c (STM-16c) Jitter Tolerance 100 10 1 1000 10000 PM5395 CRSU-4x2488 GR-253 Specification 0.1 10.2 SONET/SDH Receive Line Interface (SRLI) The four SONET/SDH receive line interface blocks perform initial byte and frame alignment on four independent incoming 2488 Mbit/s data streams based on the SONET/SDH A1/A2 framing pattern. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ ...
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While out of frame, the SRLI monitors the receive data stream for an occurrence of the A1/A2 framing pattern. The SRLI adjusts its byte and frame alignment when three consecutive A1 bytes followed by three consecutive A2 bytes occur in ...
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The RRMP also detects loss of frame (LOF) defect and loss of signal (LOS) defect. LOF is declared when an out of frame (OOF) condition exists for a total period of 3ms during which there is no continuous in frame ...
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RRMP optionally inserts line alarm indication signal (AIS-L). A maskable interrupt is activated to indicate any change in the status of out of frame (OOF), loss of frame (LOF), loss of signal (LOS), line remote defect indication (RDI-L), line alarm ...
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The line BIP monitor calculates the line BIP for a received STS-48/STM-16 frame and compares it to the B2 bytes of the following received frame. Any differences in the comparison indicate a BIP error. The monitor counts either BIP-8 or ...
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Transmit QSFI-4 Interface (Tx QSFI-4 I/F) Each of the four independent Transmit QSFI-4 Interface blocks carries the transmit data to the associated 2.488 Gbit/s data stream in nibble-wide format. The clock and data are phase locked to the associated ...
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The TIFE will always recalculate and insert the B2 byte into the frame whether state 1 or state 2 as defined by STATE[1:0] bits in Register 1040H result the B1 must always be recalculated in ...
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Figure 7 STS-48 (STM-16) in SOH, Master TRSP col 1 col 1 col 1 col 1 col 1 col 1 col 2 col 2 col ... A1 A2 row 1 B1 ... E1 row ...
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BYTE HIGHEST priority D1-D3 National Unused PLD The Z0DEF register bit defines the Z0/NATIONAL growth bytes for row #1. When Z0DEF is set to logic one, the Z0/NATIONAL bytes are defined according to ITU. When Z0DEF is set to logic ...
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SONET/SDH Transmit Line Interface (STLI) Each of the four independent SONET/SDH transmit line interface block properly formats the associated outgoing 2488 Mbit/s data stream. This block interfaces the TRSP blocks to the Transmit Line Interface block. 10.12 Transmit Line ...
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Table 8 Register Memory Map Address Register Description 0000 Identity, and Global Performance Monitor Update Trigger 0001 Master Reset 0002 Master Interrupt Status RX CH0 0003 Master Interrupt Status RX CH1 0004 Master Interrupt Status RX CH2 0005 Master Interrupt ...
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Address Register Description 1033 RSOP Reserved 1034-103F Unused TIFE 1040 TIFE Configuration 1041 TIFE Control 1042 TIFE Error Insertion Byte 0 1043 TIFE Error Insertion Byte 1 1044 TIFE Error Insertion Byte 2 1045 TIFE Error Insertion Byte 3 1046-104F ...
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Address Register Description 1082 TRSP Aux3 Error Insertion 1083 TRSP Aux2 Z0 Transmit 1084-108A TRSP Aux3 Reserved 108B-108F Unused STLI 1090 STLI Clock Configuration 1091 STLI Reserved 1092-109F Unused TXLI 10A0 TXLI Control/Status 10A1 TXLI CSU Control 10A2 TXLI Pattern ...
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Address Register Description 1126 RRMP AIS enable 1127 RRMP Section BIP Error Counter 1128 RRMP Line BIP Error Counter (LSB) 1129 RRMP Line BIP Error Counter (MSB) 112A RRMP Line REI Error Counter (LSB) 112B RRMP Line REI Error Counter ...
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Address Register Description 1187 SBER SF BERM Saturation Threshold (MSB) 1188 SBER SF BERM Declaring Threshold (LSB) 1189 SBER SF BERM Declaring Threshold (MSB) 118A SBER SF BERM Clearing Threshold (LSB) 118B SBER SF BERM Clearing Threshold (MSB) 118C SBER ...
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Address Register Description 1244 TIFE Error Insertion Byte 2 1245 TIFE Error Insertion Byte 3 1246-124F Unused TRSP 1250 TRSP Configuration 1251 TRSP Register Insertion 1252 TRSP Error Insertion 1253 TRSP Transmit J0 and Z0 1254 TRSP Transmit E1 and ...
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Address Register Description 1292-129F Unused TXLI 12A0 TXLI Control/Status 12A1 TXLI CSU Control 12A2 TXLI Pattern Register 12A3-12FF Unused CHANNEL 1 RX REGISTERS RXLI 1300 RXLI Interrupt Status 1301 RXLI Interrupt Control 1302 RXLI CRU Control 1303 RXLI CRU Clock ...
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Address Register Description 1340-1345 RRMP Reserved 3(slave) 1350-1355 RRMP Reserved 4(slave) 1336 RRMP AIS enable 2 (Slave) 1346 RRMP AIS enable 3 (Slave) 1356 RRMP AIS enable 4 (Slave) 1337-133B RRMP Reserved 2(slave) 1347-134B RRMP Reserved 3(slave) 1357-135B RRMP Reserved ...
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Address Register Description 138F SBER SD BERM Saturation Threshold (MSB) 1390 SBER SD BERM Declaring Threshold (LSB) 1391 SBER SD BERM Declaring Threshold (MSB) 1392 SBER SD BERM Clearing Threshold (LSB) 1393 SBER SD BERM Clearing Threshold (MSB) 1394-13FF Unused ...
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Address Register Description 1452 TRSP Error Insertion 1453 TRSP Transmit J0 and Z0 1454 TRSP Transmit E1 and F1 1455 TRSP Transmit D1D3 1456 TRSP Reserved 1457 TRSP Reserved 1458 TRSP Reserved 1459 TRSP Reserved 145A TRSP B1 Mask 145B-145F ...
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Address Register Description CHANNEL 2 RX REGISTERS RXLI 1500 RXLI Interrupt Status 1501 RXLI Interrupt Control 1502 RXLI CRU Control 1503 RXLI CRU Clock Training Configuration and Status 1504 RXLI PRBS Control 1505 RXLI Pattern 1506-150F Unused SRLI 1510 SRLI ...
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Address Register Description 1557-155B RRMP Reserved 4(slave) 153C-153F Unused 154C-154F Unused 155C-155F Unused RIFD 1560 RIFD Configuration 1561 RIFD Status 1562 RIFD interrupt enable 1563 RIFD interrupt status 1564 RIFD correctable error count LSB 1565 RIFD correctable error count MSB ...
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Address Register Description CHANNEL 3 TX REGISTERS QSFIM_2488 1600 QSFIM_2488 Status 1601 QSFIM_2488 Control 1602 QSFIM_2488 Reserved 1603-161F Unused 1620 Reserved 1621 Reserved 1622-162F Unused RSOP 1630 RSOP Control 1631 RSOP Interrupt Status 1632 RSOP Reserved 1633 RSOP Reserved 1634-163F ...
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Address Register Description 1659 TRSP Reserved 165A TRSP B1 Mask 165B-165F Unused 1660 TRSP Aux1 Configuration 1661 TRSP Aux1 Register Insertion 1662 TRSP Aux1 Error Insertion 1663 TRSP Aux1 Z0 Transmit 1664-166A TRSP Aux1 Reserved 166B-166F Unused 1670 TRSP Aux2 ...
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Address Register Description 1703 RXLI CRU Clock Training Configuration and Status 1704 RXLI PRBS Control 1705 RXLI Pattern 1706-170F Unused SRLI 1710 SRLI Clock Configuration 1711 SRLI Reserved 1712-171F Unused RRMP 1720 RRMP Configuration 1721 RRMP Status 1722 RRMP Interrupt ...
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Address Register Description 1761 RIFD Status 1762 RIFD interrupt enable 1763 RIFD interrupt status 1764 RIFD correctable error count LSB 1765 RIFD correctable error count MSB 1766 RIFD Line BIP error count LSB 1767 RIFD Line BIP error count MSB ...
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Normal Mode Register Description Normal mode registers are used to configure and monitor the operation of the CRSU 4x2488. Normal mode registers (as opposed to test mode registers) are selected when A[13] is low. Notes on Normal Mode Register ...
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... TYPE[4:0] The TYPE bits can be read to distinguish the CRSU-4X2488 from the other members of the family of devices. The TYPE[4:0] register for the PM5395 CRSU -4X2488 is 00010. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ ...
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TIP The TIP bit is set to logic one when the performance meter registers are being loaded. Writing to this register with the DRESET_CH[n] bit in register 0001H equal to logic 0 initiates an accumulation interval transfer and loads all ...
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Register 0001H: Master Reset Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R Bit ...
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TX_ARSTB_CH[3:0] The Transmit Analog Reset bit. When TX_ARSTB_CH[3:0] is set to logic zero all 2.488 GHz Line Side analog circuitry in the transmit side of channel n is placed into reset. This bit is not self-clearing. Therefore, a logic one ...
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Register 0002H: Master Interrupt Status RX CH0 Bit Type Function Bit 15 R/W INT_RX_CH0_EN Bit 14 R Unused Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 ...
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RIFD_INT_0 The RIFD Interrupt Status for channel 0 indicates an interrupt from the Receive In-band FEC Decoder (RIFD) has occurred. The interrupt status bit is set to logic 1 to indicate a pending interrupt. The interrupt status bit is independent ...
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Register 0003H: Master Interrupt Status RX CH1 Bit Type Function Bit 15 R/W INT_RX_CH1_EN Bit 14 R Unused Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 91
RIFD_INT_1: The RIFD Interrupt Status for channel 1 indicates an interrupt from the Receive In-band FEC Decoder (RIFD) has occurred. The interrupt status bit is set to logic 1 to indicate a pending interrupt. The interrupt status bit is independent ...
Page 92
Register 0004H: Master Interrupt Status RX CH2 Bit Type Function Bit 15 R/W INT_RX_CH2_EN Bit 14 R Unused Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 93
RIFD_INT_2 The RIFD Interrupt Status for channel 2 indicates an interrupt from the Receive In-band FEC Decoder (RIFD) has occurred. The interrupt status bit is set to logic 1 to indicate a pending interrupt. The interrupt status bit is independent ...
Page 94
Register 0005H: Master Interrupt Status RX CH3 Bit Type Function Bit 15 R/W INT_RX_CH3_EN Bit 14 R Unused Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 95
RIFD_INT_3 The RIFD Interrupt Status for channel 3 indicates an interrupt from the Receive In-band FEC Decoder (RIFD) has occurred. The interrupt status bit is set to logic 1 to indicate a pending interrupt. The interrupt status bit is independent ...
Page 96
Register 0006H: Master Interrupt Status TX CH0 Bit Type Function Bit 15 R/W INT_TX_CH0_EN Bit 14 R Unused Bit 13 R TXLI_INT_0 Bit 12 R Unused Bit 11 R RSOP_INT_0 Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 97
INT_TX_CH0_EN The interrupt enable for the Transmitter section of Channel 0 controls the assertion of the interrupt (INTB) output pin. When a logic 1 is written to INT_TX_CH0_EN, the TXLI_INT_0 or RSOP_INT_0 pending interrupt will assert the interrupt (INTB) output. ...
Page 98
Register 0007H: Master Interrupt Status TX CH1 Bit Type Function Bit 15 R/W INT_TX_CH1_EN Bit 14 R Unused Bit 13 R TXLI_INT_1 Bit 12 R Unused Bit 11 R RSOP_INT_1 Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 99
INT_TX_CH1_EN The interrupt enable for the Transmitter section of Channel 1 controls the assertion of the interrupt (INTB) output pin. When a logic 1 is written to INT_TX_CH1_EN, the TXLI_INT_1 or RSOP_INT_1 pending interrupt will assert the interrupt (INTB) output. ...
Page 100
Register 0008H: Master Interrupt Status TX CH2 Bit Type Function Bit 15 R/W INT_TX_CH2_EN Bit 14 R Unused Bit 13 R TXLI_INT_2 Bit 12 R Unused Bit 11 R RSOP_INT_2 Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 101
INT_TX_CH2_EN The interrupt enable for the Transmitter section of Channel 2 controls the assertion of the interrupt (INTB) output pin. When a logic 1 is written to INT_TX_CH2_EN, the TXLI_INT_2 or RSOP_INT_2 pending interrupt will assert the interrupt (INTB) output. ...
Page 102
Register 0009H: Master Interrupt Status TX CH3 Bit Type Function Bit 15 R/W INT_TX_CH3_EN Bit 14 R Unused Bit 13 R TXLI_INT_CH3 Bit 12 R Unused Bit 11 R RSOP_INT_CH3 Bit 10 R Unused Bit 9 R Unused Bit 8 ...
Page 103
INT_TX_CH3_EN The interrupt enable for the Transmitter section of Channel 3 controls the assertion of the interrupt (INTB) output pin. When a logic 1 is written to INT_TX_CH3_EN, the TXLI_INT_3 or RSOP_INT_3 pending interrupt will assert the interrupt (INTB) output. ...
Page 104
Register 000AH: Channel Interrupt Status Bit Type Function Bit 15 R TX_INT_CH3 Bit 14 R TX_INT_CH2 Bit 13 R TX_INT_CH1 Bit 12 R TX_INT_CH0 Bit 11 R RX_INT_CH3 Bit 10 R RX_INT_CH2 Bit 9 R RX_INT_CH1 Bit 8 R RX_INT_CH0 ...
Page 105
TX_INT_CH[3:0] The Transmit Interrupt Status for channel 3..0 indicates an interrupt in the Master Interrupt Status TX CH3..0 Register is active. The interrupt status bit is set to logic 1 to indicate a any bit in register is set. Software ...
Page 106
Register 000BH: Configuration Bit Type Function Bit 15 R Unused Bit 14 R/W SYNC_ERR_INV Bit 13 R/W PHASE_ERR_INV Bit 12 R/W WCIMODE Bit 11 R/W Reserved Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 R/W Reserved Bit 7 ...
Page 107
Register 000CH: Bypass and fiber order Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 R/W TIFE_BYPASS_CH3 Bit 10 R/W TIFE_BYPASS _CH2 Bit 9 R/W TIFE_BYPASS _CH1 Bit ...
Page 108
TIFE_BYPASS_CH[3:0] This register bit controls the state of the TIFE. When TIFE_BYPASS_CH[3:0] is set to logic one the TIFE is placed in a zero-delay mode wherein the data and frame pulse outputs are equal to the data and frame pulse ...
Page 109
Register 000DH: Diagnostic Loopback and ICO control Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 R/W Reserved Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 ...
Page 110
SPLE_CH[3:0] The System Side Parallel Loopback, SPLE bit enables the CRSU 4x2488 loopback where the transmitter STLI block is directly connected to its receiver SRLI block. This bit loops the data received on theQSFI-4 TXDATA interface back theQSFI-4 RXDATA signals ...
Page 111
Register 000EH: Clock Control Bit Type Function Bit 15 R/W KILL_RRMP_CLK_CH3 Bit 14 R/W KILL_RRMP_CLK_CH2 Bit 13 R/W KILL_RRMP_CLK_CH1 Bit 12 R/W KILL_RRMP_CLK_CH0 Bit 11 R/W KILL_RIFD_CLK_CH3 Bit 10 R/W KILL_RIFD_CLK_CH2 Bit 9 R/W KILL_RIFD_CLK_CH1 Bit 8 R/W KILL_RIFD_CLK_CH0 Bit ...
Page 112
KILL_RIFD_CLK_CH[3:0] The Kill the RIFD clock register bit stops the RIFD block clock of the selected channel. When KILL_RIFD_CLK_CH[3:0] is enabled the clock to the RIFD is held at a constant value. Stopping the clock prevents the block from operating ...
Page 113
Register 000FH: Bypass and Loop-across Bit Type Function Bit 15 R/W LBEN_CH3 Bit 14 R/W LBEN_CH2 Bit 13 R/W LBEN_CH1 Bit 12 R/W LBEN_CH0 Bit 11 R/W CHLBEN_CH3 Bit 10 R/W CHLBEN_CH2 Bit 9 R/W CHLBEN_CH1 Bit 8 R/W CHLBEN_CH0 ...
Page 114
Receive Path of Channel 0 to Transmit Path of Channel 1 Receive Path of Channel 3 to Transmit Path of Channel 2 Receive Path of Channel 2 to Transmit Path of Channel 3 When CHLBEN_CH[n] is logic 1 the Data ...
Page 115
Register 0010H: Diagnostics#1 Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 R/W Reserved Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 R/W Reserved Bit 7 ...
Page 116
Register 0011H: Channel 3 and 2 SALM Enables Bit Type Function Bit 15 R/W OOF_EN_CH3 Bit 14 R/W LOS_RRMP_EN_CH3 Bit 13 R/W LOS_RXLI_EN_CH3 Bit 12 R/W LOF_EN_CH3 Bit 11 R/W LAIS_EN_CH3 Bit 10 R/W LRDI_EN_CH3 Bit 9 R/W SF_EN_CH3 Bit ...
Page 117
LRDI_EN_CH2 The SALM[2] Line Remote Defect Indication enable. The LRDI_EN_CH2 enables the reporting of LRDI alarms on the section alarm SALM[2] output pin. When LRDI_EN_CH2 is set to logic one LRDI alarms from the RRMP will set the SALM[2] pin ...
Page 118
OOF_EN_CH2 The SALM[2] Out Of Frame Status enable. The OOF_EN_CH2 enables the reporting of OOF alarms on the section alarm SALM[2] output pin. When OOF_EN_CH2 is set to logic one OOF alarms from the RRMP will set the SALM[2] pin ...
Page 119
LOF_EN_CH3 The SALM[3] Loss Of Frame Status enable. The LOF_EN_CH3 enables the reporting of LOF alarms on the section alarm SALM[3] output pin. When LOF_EN_CH3 is set to logic one LOF alarms from the RRMP will set the SALM[3] pin ...
Page 120
Register 0012H: Channel 1 and 0 SALM ENABLES Bit Type Function Bit 15 R/W OOF_EN_CH1 Bit 14 R/W LOS_RRMP_EN_CH1 Bit 13 R/W LOS_RXLI_EN_CH1 Bit 12 R/W LOF_EN_CH1 Bit 11 R/W LAIS_EN_CH1 Bit 10 R/W LRDI_EN_CH1 Bit 9 R/W SF_EN_CH1 Bit ...
Page 121
LRDI_EN_CH0 The SALM[0] Line Remote Defect Indication enable. The LRDI_EN_CH0 enables the reporting of LRDI alarms on the section alarm SALM[0] output pin. When LRDI_EN_CH0 is set to logic one LRDI alarms from the RRMP will set the SALM[0] pin ...
Page 122
OOF_EN_CH0 The SALM[0] Out Of Frame Status enable. The OOF_EN_CH0 enables the reporting of OOF alarms on the section alarm SALM[0] output pin. When OOF_EN_CH0 is set to logic one OOF alarms from the RRMP will set the SALM[0] pin ...
Page 123
LOF_EN_CH1 The SALM[1] Loss Of Frame Status enable. The LOF_EN_CH1 enables the reporting of LOF alarms on the section alarm SALM[1] output pin. When LOF_EN_CH1 is set to logic one LOF alarms from the RRMP will set the SALM[1] pin ...
Page 124
Register 0013H: TXENB Control Bit Type Function Bit 15 R/W LCRUTO_EN_CH3 Bit 14 R/W LCRUTO_EN_CH2 Bit 13 R/W LCRUTO_EN_CH1 Bit 12 R/W LCRUTO_EN_CH0 Bit 11 R/W ANALOG_QSFI-4_ENB Bit 10 R/W TXENB_CH3 Bit 9 R/W TXENB_CH2 Bit 8 R/W TXENB_CH1 Bit ...
Page 125
LCRUTO_EN_CH[3:0] 2.488 GHz Line Side Interface Clock enable. When the LCRUTO_EN_CH[n] is set to logic ‘1’ the LCRUTO[n] clock output pins for channel n are enabled; a 155Mhz recovered clock will be sourced from LCRUTO pins. When set to logic ...
Page 126
... CHIPID[0] CHIPID[15:0] The Chip Identification Code provides a software test of the device identity. The CHIPID[15:0] is set to 5395H to identify the device as the PM5395 CRSU 4x2488. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet ...
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Channel Register Map The CRSU 4x2488 contains four channels in total. The order and number of registers for each channel is the same. The starting location for each channel is offset by 200H. For example if the programmer wanted ...
Page 128
Channel 0 Register Map: Register 1000H: QSFIM_2488 Status Bit Type Function Bit 15 Unused Bit 14 Unused Bit 13 Unused Bit 12 Unused Bit 11 Unused Bit 10 Unused Bit 9 Unused Bit 8 Unused Bit 7 Unused Bit 6 ...
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Register 1001H: QSFIM_2488 Control Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 — Unused Bit 10 R/W RX_ESTORE_RST Bit 9 R/W RX_ ESTORE_ERR_EN Bit 8 R/W Reserved ...
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RX_ESTORE_ERR_EN The Receive Elastic Store Error Enable bit connects the RX_ESTORE_ERR_I status bit to the QSFIM_INT_CH1 bit 4 Register 000AH. When RX_ESTORE_ERR_EN is set to logic one, the QSFIM_INT_CH1 bit is set to logic one upon assertion of the RX_ESTORE_ERR_I ...
Page 131
Register 1002H: QSFIM_2488 Reserved Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 R/W Reserved Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 R/W Reserved Bit ...
Page 132
Register 1030H: RSOP Control Bit Type Function Bit 15 — Unused Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 — Unused Bit 10 — Unused Bit 9 — Unused Bit 8 — Unused Bit ...
Page 133
Register 1031H: RSOP Interrupt Status Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 — Bit 7 — Bit 6 R Bit 5 R ...
Page 134
Register 1040H: TIFE Configuration Bit Type Function Bit 15 R Unused Bit 14 R Unused Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 R Unused Bit ...
Page 135
Register 1041H: TIFE Control Bit Type Function Bit 15 R/W HS_EN Bit 14 R/W FSI_MASK_EN Bit 13 R Unused Bit 12 R Unused Bit 11 R Unused Bit 10 R Unused Bit 9 R Unused Bit 8 R Unused Bit ...
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HS_EN The handshake enable bit. This bit enables the seven-frame FSI handshaking defined in T1X1.5/99-218R2 In band FEC for SONET specification (See the list of references in Section 2 of this document). When HS_EN is set to logic ‘1’, the ...
Page 137
Register 1042H: TIFE Error Insertion Byte 0 Bit Type Function Bit 15 R/W INSERT_EN_0 Bit 14 R Unused Bit 13 R Unused Bit 12 R/W PARAM_A_0[10] Bit 11 R/W PARAM_A_0[9] Bit 10 R/W PARAM_A_0[8] Bit 9 R/W PARAM_A_0[7] Bit 8 ...
Page 138
INSERT_EN_0 The byte 0 Insertion enable bit. Setting this bit ‘1’ enables inverting the byte defined by the PARAM_B_0[1:0] and PARAM_A_0[10:0] fields. When this bit is set to logic '0' the PARAM_B_0[1:0] and PARAM_A_0[10:0] fields are ignored and no byte ...
Page 139
Register 1043H: TIFE Error Insertion Byte 1 Bit Type Function Bit 15 R/W INSERT_EN_1 Bit 14 R Unused Bit 13 R Unused Bit 12 R/W PARAM_A_1[10] Bit 11 R/W PARAM_A_1[9] Bit 10 R/W PARAM_A_1[8] Bit 9 R/W PARAM_A_1[7] Bit 8 ...
Page 140
INSERT_EN_1 The byte 1 Insertion enable bit. Setting this bit ‘1’ enables inverting the byte defined by the PARAM_B_1[1:0] and PARAM_A_1[10:0] fields. When this bit is set to logic '0' the PARAM_B_1[1:0] and PARAM_A_1[10:0] fields are ignored and no byte ...
Page 141
Register 1044H: TIFE Error Insertion Byte 2 Bit Type Function Bit 15 R/W INSERT_EN_2 Bit 14 R Unused Bit 13 R Unused Bit 12 R/W PARAM_A_2[10] Bit 11 R/W PARAM_A_2[9] Bit 10 R/W PARAM_A_2[8] Bit 9 R/W PARAM_A_2[7] Bit 8 ...
Page 142
INSERT_EN_2 The byte 2 Insertion enable bit. Setting this bit ‘1’ enables inverting the byte defined by the PARAM_B_2[1:0] and PARAM_A_2[10:0] fields. When this bit is set to logic '0' the PARAM_B_2[1:0] and PARAM_A_2[10:0] fields are ignored and no byte ...
Page 143
Register 1045H: TIFE Error Insertion Byte 3 Bit Type Function Bit 15 R/W INSERT_EN_3 Bit 14 R Unused Bit 13 R Unused Bit 12 R/W PARAM_A_3[10] Bit 11 R/W PARAM_A_3[9] Bit 10 R/W PARAM_A_3[8] Bit 9 R/W PARAM_A_3[7] Bit 8 ...
Page 144
INSERT_EN_3 The byte 3 Insertion enable bit. Setting this bit ‘1’ enables inverting the byte defined by the PARAM_B_3[1:0] and PARAM_A_3[10:0] fields. When this bit is set to logic '0' the PARAM_B_3[1:0] and PARAM_A_3[10:0] fields are ignored and no byte ...
Page 145
Register 1050H: TRSP Configuration Bit Type Function Bit 15 — Unused Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 R/W Reserved Bit 10 R/W LREIEN (see attached note) APSEN (see attached note) Bit 9 ...
Page 146
J0Z0INCEN The J0 and Z0 increment enable (J0Z0INCEN) bit controls the insertion of an incremental pattern in the section trace and Z0 growth bytes. When J0ZOINCEN is set to logic 1, the corresponding STS-1/STM-0 path # is inserted in the ...
Page 147
Register 1051H: TRSP Register Insertion Bit Type Function Bit 15 R/W UNUSEDV Bit 14 R/W UNUSEDEN Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 — Unused Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 R/W Reserved ...
Page 148
E1REGEN The E1 register enable (E1REGEN) bit controls the insertion of section order wire in the data stream. When E1REGEN is set to logic 1, the section order wire from the TRSP Transmit E1 and F1 register is inserted in ...
Page 149
Register 1052H: TRSP Error Insertion Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W ...
Page 150
LOSINS The LOS insertion (LOSINS) bit is used to force a loss of signal condition in the data stream. When LOSINS is set to logic 1, the data steam is set to all zero (after scrambling) to force a loss ...
Page 151
Register 1053H: TRSP Transmit J0 and Z0 Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit ...
Page 152
Register 1054H: TRSP Transmit E1 and F1 Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit ...
Page 153
Register 1055H: TRSP Transmit D1D3 Bit Type Function Bit 15 R/W D1D3V[7] Bit 14 R/W D1D3V[6] Bit 13 R/W D1D3V[5] Bit 12 R/W D1D3V[4] Bit 11 R/W D1D3V[3] Bit 10 R/W D1D3V[2] Bit 9 R/W D1D3V[1] Bit 8 R/W D1D3V[0] ...
Page 154
Register 1056H: TRSP Reserved Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit ...
Page 155
Register 1057H: TRSP Reserved Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit ...
Page 156
Register 1058H: TRSP Reserved Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit ...
Page 157
Register 1059H: TRSP Reserved Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit ...
Page 158
Register 105AH: TRSP Transmit B1Mask Bit Type Function Bit 15 R/W B1MASK[7] Bit 14 R/W B1MASK[6] Bit 13 R/W B1MASK[5] Bit 12 R/W B1MASK[4] Bit 11 R/W B1MASK[3] Bit 10 R/W B1MASK[2] Bit 9 R/W B1MASK[1] Bit 8 R/W B1MASK[0] ...
Page 159
Register 1060H: TRSP Aux1 Configuration Register 1070H: TRSP Aux2 Configuration Register 1080H: TRSP Aux3 Configuration Bit Type Function Bit 15 — Unused Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 R/W Reserved Bit 10 ...
Page 160
Register 1061H: TRSP Aux1 Register Insertion Register 1071H: TRSP Aux2 Register Insertion Register 1081H: TRSP Aux3 Register Insertion Bit Type Function Bit 15 R/W Reserved Bit 14 R/W Reserved Bit 13 R/W Reserved Bit 12 R/W Reserved Bit 11 — ...
Page 161
Register 1062H: TRSP Aux1 Error Insertion Register 1072H: TRSP Aux2 Error Insertion Register 1082H: TRSP Aux3 Error Insertion Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 ...
Page 162
Register 1063H: TRSP Aux1 Transmit Z0 Register 1073H: TRSP Aux2 Transmit Z0 Register 1083H: TRSP Aux3 Transmit Z0 Bit Type Bit 15 R/W Bit 14 R/W Bit 13 R/W Bit 12 R/W Bit 11 R/W Bit 10 R/W Bit 9 ...
Page 163
Register 1064-106AH: TRSP Aux1 Reserved Register 106BH- 106FH Unused Register 1074-107AH: TRSP Aux2 Reserved Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet Released 163 ...
Page 164
Register 107BH- 107FH unused Register 1084-108AH: TRSP Aux3 Reserved Register 108BH- 108FH unused Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001972, Issue 5 CRSU™ 4x2488 Telecom Standard Product Data Sheet Released 164 ...
Page 165
Register 1090H: STLI Clock Configuration Bit Type Function Bit 15 R/W Reserved Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 — Unused Bit 10 — Unused Bit 9 — Unused Bit 8 — Unused ...
Page 166
Register 10A0H: TXLI Control/Status Bit Type Function Bit 15 R ROOL_I Bit 14 R Reserved Bit 13 — Unused Bit 12 R Reserved Bit 11 R/W Reserved Bit 10 — Unused Bit 9 — Unused Bit 8 R/W TX_DISABLE Bit ...
Page 167
LPLE_TX The Line Side Parallel Loopback enable loops the recovered data and clock from the RXD[0]+/- input pin to the transmit output, TXD[0]+/- pin. When this bit is set to logic 1 data from the 2.488 Gbs line side Receiver ...
Page 168
TX_DISABLE The Transmitter Disable bit controls the output of the TXD[0]+/- pins of the CRSU 4x2488. If TX_DISABLE is set to logic '1' the output on the TXD[0]+/- pins is forced to the active high state. If TX_DISABLE is set ...
Page 169
Register 10A1H: TXLI CSU Control Bit Type Function Bit 15 R/W RECCLK_SEL Bit 14 R/W Reserved Bit 13 R/W CSU_RESET Bit 12 R/W Reserved Bit 11 R/W TX2488_ENABLE Bit 10 R/W Reserved Bit 9 R/W Reserved Bit 8 R/W Reserved ...
Page 170
LOOP-TIME MODE divide by 1 (DEFAULT) Note: In non-loop time operation (LOOPTIMEB set to logic one) this bit must be set to logic one (divide insure proper operation. In loop-time ...
Page 171
CSU_RESET The Clock Source Unit Reset provides a complete reset of the CSU2488 Analog Block Circuit. When set to ‘1’ this bit forces the ABC to a known initial state. While the bit is set to ‘1’ the functionality of ...
Page 172
Register 10A2H: TXLI Pattern Register Bit Type Function Bit 15 R/W FPATT[15] Bit 14 R/W FPATT[14] Bit 13 R/W FPATT[13] Bit 12 R/W FPATT[12] Bit 11 R/W FPATT[11] Bit 10 R/W FPATT[10] Bit 9 R/W FPATT[9] Bit 8 R/W FPATT[8] ...
Page 173
Register 1100H: RXLI Interrupt Status Bit Type Function Bit 15 R CRU_CLOCK Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 — Unused Bit 10 — Unused Bit 9 — Unused Bit 8 — Unused ...
Page 174
DOOL_I The recovered data out of lock status indicates the clock recovery unit (CRU) phase locked loop is unable to recover and lock to the input data stream. DOOL_I is a logic one if the divided down recovered 2.488 GHz ...
Page 175
PRBS_SYNC_I The PRBS Synchronization bit indicates that a change in the status of PRBS Monitor has occurred. The comparison is made between the incoming data from the RXD[0]+/- and the PRBS pattern generated locally. The PRBS_SYNC_I is set high when ...
Page 176
Register 1101H: RXLI Interrupt Control Bit Type Function Bit 15 R/W SD_DISABLE Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 — Unused Bit 10 — Unused Bit 9 — Unused Bit 8 — Unused ...
Page 177
FIFO_ERROR_EN The FIFO Error Enable bit connects the FIFO_ERROR_I status bit to the RXLI_INT_0 bit of the Master Interrupt Status RX CH0 Register, 0002H . When FIFO_ERROR_EN is set to logic one, the RXLI_INT_0 bit will be set to logic ...
Page 178
Register RXLI 1102H: CRU Control Bit Type Function Bit 15 R/W Reserved Bit 14 R/W CRU_RESET Bit 13 R/W Reserved Bit 12 R/W RX2488_ENABLE Bit 11 R/W Reserved Bit 10 R/W LOCK_TO_REF Bit 9 R/W Reserved Bit 8 R/W Reserved ...
Page 179
SDLE The Serial Diagnostic Loopback Enable (SDLE) bit, when set to ‘1’, loops the data from the transmit line side PISO to the receive side SIPO. Setting the SDLE to logic '1' is equivalent to connecting the TXD[0]+/- output pins ...
Page 180
Register 1103H: RXLI CRU Clock Training Configuration and Status Bit Type Function Bit 15 R/W LOS_COUNT[4] Bit 14 R/W LOS_COUNT[3] Bit 13 R/W LOS_COUNT[2] Bit 12 R/W LOS_COUNT[1] Bit 11 R/W LOS_COUNT[0] Bit 10 R/W LOSEN Bit 9 R/W LPLE_RX ...
Page 181
DOOLV The recovered data out of lock status indicates that the clock recovery phase locked loop is unable to recover and lock to the input data stream. DOOLV is logic one if the divided down recovered clock frequency is not ...
Page 182
LOS_COUNT[4:0] The Loss of signal 1’s/0’s transition detector count value. This field sets the value for the number of consecutive all-zeros or all-ones pattern that will force the CRU out of the LOCK TO DATA State. The value in the ...
Page 183
Register 1104H: RXLI PRBS Control Bit Type Function Bit 15 R PRBS_ERR_CNT[7] Bit 14 R PRBS_ERR_CNT[6] Bit 13 R PRBS_ERR_CNT[5] Bit 12 R PRBS_ERR_CNT[4] Bit 11 R PRBS_ERR_CNT[3] Bit 10 R PRBS_ERR_CNT[2] Bit 9 R PRBS_ERR_CNT[1] Bit 8 R PRBS_ERR_CNT[0] ...
Page 184
CLEAR_ERR_CNT The Clear Error Count bit clears the PRBS word error count value. When logic 1 is written to this bit the PRBS word error count register is reset to zero. When set to logic 0 the counter operates normally. ...
Page 185
Register 1105H: RXLI Pattern Bit Type Function Bit 15 R/W FPATT[15] Bit 14 R/W FPATT[14] Bit 13 R/W FPATT[13] Bit 12 R/W FPATT[12] Bit 11 R/W FPATT[11] Bit 10 R/W FPATT[10] Bit 9 R/W FPATT[9] Bit 8 R/W FPATT[8] Bit ...
Page 186
Register 1106H – 110FH: RXLI Reserved Register 1110H: SRLI Clock Configuration Bit Type Function Bit 15 R/W Reserved Bit 14 — Unused Bit 13 — Unused Bit 12 — Unused Bit 11 — Unused Bit 10 — Unused Bit 9 ...
Page 187
Register 1120H: RRMP Configuration Bit Type Function Bit 15 R BUSY Bit 14 — Unused Bit 13 — Unused Bit 12 R/W LREIBLK Bit 11 R/W Reserved Bit 10 R/W LBIPECNTBLK Bit 9 R/W LBIPEACCBLK Bit 8 R/W Reserved Bit ...
Page 188
LRDI3 The line remote defect indication detection (LRDI3) bit selects the Line RDI detection algorithm. When LRDI3 is set to logic 1, Line RDI is declared when a 110 pattern is detected in bits 6,7,8 of the K2 byte for ...
Page 189
BUSY The BUSY (BUSY) bit reports the status of the transfer of section BIP, line BIP and line REI error counters to the holding registers. BUSY is set to logic 1 upon writing to the holding register addresses or by ...
Page 190
Register 1121H: RRMP Status Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 — Bit 7 — Bit 6 — Bit 5 R Bit ...
Page 191
LAISV The LAISV bit reflects the current status of the line alarm indication signal defect. The AIS- L defect is declared when the 111 pattern is detected in bits 6,7 and 8 of the K2 byte for three or five ...
Page 192
Register 1122H: RRMP Interrupt Enable Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 R/W Bit 9 R/W Bit 8 R/W Bit 7 R/W Bit 6 R/W Bit 5 R/W ...
Page 193
Register 1123H: RRMP Interrupt Status Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 R ...
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LAISI The line alarm indication signal interrupt status (LAISI) bit is an event indicator. LAISI is set to logic 1 to indicate any change in the status of LAISV. The interrupt status bit is independent of the interrupt enable bit. ...
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SBIPEI The section BIP error interrupt status (SBIPEI) bit is an event indicator. SBIPEI is set to logic 1 to indicate a section BIP error. The interrupt status bit is independent of the interrupt enable bit. If the WCIMODE bit ...
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Register 1124H: RRMP Receive APS Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit 5 R ...
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Register 1125H: RRMP Receive SSM Bit Type Bit 15 R/W Bit 14 R/W Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 — Bit 7 R Bit 6 R Bit 5 R ...
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Register 1126H: RRMP AIS Enable Bit Type Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 — Bit 7 — Bit 6 — Bit 5 — ...
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K2AIS The K2 line AIS (K2AIS) bit restricts line AIS to the K2 byte. When K2AIS is set to logic 1, line AIS is only inserted in bits 6, 7 and 8 of the K2 byte. When K2AIS is set ...
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Register 1127H: RRMP Section BIP Error Counter Bit Type Bit 15 R Bit 14 R Bit 13 R Bit 12 R Bit 11 R Bit 10 R Bit 9 R Bit 8 R Bit 7 R Bit 6 R Bit ...