FC80960HD Intel Corporation, FC80960HD Datasheet
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Intel i960 RM/RN I/O Processor Design Guide April 2002 Order Number: 273139-004 ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Other brands and names are the property of their respective owners. Design Guide ...
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Contents 1.0 Introduction ................................................................................................................................... 9 ® 2.0 Intel 80960RM/RN Processor Ball Map...................................................................................... 9 ® 2.1 Intel 80960RM/RN Processor PBGA Signal Ball Map .................................................10 3.0 Routing Guidelines .....................................................................................................................11 3.1 Trace Length Limits .......................................................................................................11 ® 4.0 Intel 80960RM/RN Processor Memory Subsystem ..................................................................12 ...
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Intel i960 RM/RN I/O Processor 12.3 JTAG Connector and Test Interface .............................................................................. 48 ® ® 12.3.1 Intel i960 RM/RN I/O Processor JTAG Emulator ..................................................... 48 ® ® 12.3.2 Intel i960 RM/RN I/O Processor Target Debug Interface Connector ....................... ...
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Figures 2-1 540L H-PBGA Diagram (Bottom View).......................................................................................10 3-2 Examples of Stubless and Short Stub Traces ............................................................................11 4-3 4 Mbyte Flash Memory System ..................................................................................................13 4-4 Dual-Bank SDRAM Memory Subsystem ....................................................................................15 4-5 SDRAM DIMM Layout Topology #1............................................................................................17 4-6 SDRAM DIMM Layout Topology ...
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Intel i960 RM/RN I/O Processor 15-50 Logic Analyzer I/F Schematic ..................................................................................................... 81 15-51 SDRAM 168-Pin DIMM Schematic ............................................................................................. 82 15-52 Secondary PCI/80960 Core Schematic ...................................................................................... 83 15-53 Secondary PCI Bus 1/2 Schematic ............................................................................................ 84 15-54 Secondary PCI Bus ...
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Tables 4-1 Flash Interface Signals ...............................................................................................................12 4-2 ROM, SRAM, or Flash Wait State Profile Programming.............................................................13 4-3 SDRAM Interface Signals ...........................................................................................................14 4-4 Drive Strength Programmability Options ....................................................................................16 4-5 DCLKIN Routing and Loading Requirements.............................................................................21 4-6 SDRAM Clock Buffer Information ...............................................................................................22 ® 5-7 ...
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Intel i960 RM/RN I/O Processor Revision History Rev Date 004 04/2002 003 08/2000 002 06/2000 1.0 06/1998 0.9 12/10/97 8 Description of Changes • Changed “Thermal Recommendations” section. • Added schematics. • Updated Trademarks and Branding. • Updated ...
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Introduction This design guide addresses design considerations for designing with either the Intel I/O processor or the Intel in design constraints between the two processors is clarified. The i960 RN I/O Processor is an Intel I/O processor supporting both ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Ball Map Figure 2-1. 540L H-PBGA Diagram (Bottom View ...
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Routing Guidelines The order in which signals are routed first and last varies from designer to designer. Some prefer to route all clock signals first, while others prefer to route all high speed bus signals first. Either order can ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem ® 4.0 Intel 80960RM/RN Processor Memory Subsystem The RM/RN I/O processor RM/RN I/O processor • Mbytes of 8-bit Flash, ROM, or SRAM • Between 8 and ...
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Layout Guidelines Figure 4-3 illustrates how two Flash devices would interface to the memory controller. The Flash subsystem requires an external latch for address and data demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9]. Figure 4-3. 4 Mbyte ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem 4.2 SDRAM Guidelines The RM/RN I/O processor SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128 Mbytes of ECC protected memory. For low-cost ...
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Layout Guidelines The SDRAM subsystem may be implemented with: • two banks directly connected on the printed circuit board (32, 64 bits wide) • two 168-pin DIMM sockets (64-bit data bus with or ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem The drive strengths for the SDRAM signals are independently programmable using the SDCR register. Table 4-4 lists some example SDRAM configurations and how the SDCR should be programmed. The ...
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Figure 4-5. SDRAM DIMM Layout Topology #1 Inte l® 809 60R I Figure 4-6. SDRAM DIMM Layout Topology # l® ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-7. Address and Control Topology for Two Discrete SDRAM Devices Intel® 80960RM /RN I/O Processor Figure 4-8. Address and Control Topology for Four or More Discrete SDRAM Devices ...
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Figure 4-9. Data and DQM Topology for Discrete SDRAM Devices l® The address and ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem 4.2.2 SDRAM Clocking and Clock Buffer Specifications The MCU provides one clock (DCLKOUT) to the SDRAM memory subsystem with a 66 MHz frequency. The 72-bit, 2-bank SDRAM DIMM specification ...
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DCLKOUT and the clock buffer outputs may be between 1 and 8 inches. Each of the four clock buffer outputs must be equal in length. Refer to capacitance requirements. DCLKIN requires an external capacitor to match the loading seen on ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Any memory configuration using four or more discrete SDRAM components directly on the board must adhere to the same routing requirements specified in the 4-Clock 66 MHz 72-bit ECC ...
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SDRAM Power Failure Guidelines SDRAM technology provides a simple way of enabling data preservation through the self-refresh command. When the memory controller issues this command, the SDRAM refreshes itself autonomously with internal logic and timers. The SDRAM device remains ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Memory Subsystem Figure 4-13. External Power Failure Logic in the System Memory Controller The implementation illustrated in The edge detect state machine activates the pull-down when the MCU deasserts SCKE[1:0]. As ...
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Interrupt Routing As stated in the PCI Local Bus Specification, Revision 2.1 and the PCI-to-PCI Bridge Architecture Specification, Revision 1.0, interrupt routing is system-specific. In general, the BIOS maps the device’s interrupt line to the originates from the IDSEL ...
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Intel® i960® RM/RN I/O Processor Interrupt Routing ® 5.2 Intel 80960RM/RN Processor Implementation on an Add-in Card When designing the address and interrupt routing. Figure 5-14. Example Secondary PCI Connector Interrupt Routing Intel® 80960RM/RN Processor S_INTD:A# S_AD31:0 NOTE: Secondary PCI ...
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Clocking Guidelines RM/RN I/O processor primary PCI bus and the secondary PCI bus are referenced to the P_CLK input. The system must provide clocks for any devices on the secondary PCI bus and ensure that system level goals for ...
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Intel® i960® RM/RN I/O Processor Clocking Guidelines 6.2 Layout Guidelines for Motherboards For motherboard implementations, the designer has much more flexibility with PCI clocking, primarily related to controlling the central clock resources. Skew requirements for the motherboard are more stringent ...
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Clock Vendors The low-skew clock buffer components in nor a warranty of the performance of the listed product and/or company. Table 6-8. Low Skew Clock Buffer Information Manufacturer Design Guide Table 6-8 are suggested. This is neither an endorsement ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors ® 7.0 Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 7-9 through Table 7-11 and the recommended resistor values. Table 7-9. Memory Controller, Core and JTAG Signals ...
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Intel Table 7-11. PCI Signals (Sheet Signal S_ FRAME# S_ STOP# S_ IRDY# S_ INTA# S_ INTB# S_ INTC# S_ INTD# XINT4# XINT5# S_ REQ0# S_ REQ1# S_ REQ2# S_ REQ3# S_ REQ4# S_ REQ5# S_AD[63:32] S_C/BE[7:4]# ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors ® 8.0 Intel 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 8-12 through and the recommended resistor values. Table 8-12. Memory Controller, Core and JTAG Signals Signal RAD[6]/RST_MODE# ...
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Intel Table 8-14. PCI Signals (Sheet (Sheet Signal S_ FRAME# S_ STOP# S_ IRDY# S_ INTA# S_ INTB# S_ INTC# S_ INTD# XINT4# XINT5# S_ REQ0# S_ REQ1# S_ REQ2# S_ REQ3# S_ REQ4# ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations ® 9.0 Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.1 Providing 3 System In most system ...
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Figure 9-17. Creating a Power “Island” 3.3V island Design Guide ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations Connection Point for 3.3V Source Intel® i960® RM/RN I/O Processor Gap in Plane 5V Plane 35 ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.2 Choosing a Power Source The primary concern that must be addressed when selecting a power source is the maximum load current requirement. The ...
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PCI Adapter Card Power Source Currently, PCI Adapter card vendors cannot rely on the PCI connector to provide 3.3V. Hence, any adapter card designed with the the processor power supply. 9.4 V Pin Requirement (V CC5REF In mixed voltage ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.5 V Pins Requirement CCPLL To reduce clock skew on the processor, the V isolated on the pinout. The low-pass filter, shown in and ...
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FAIL# Many applications use a light emitting diode (LED) to indicate when the FAIL# pin is low (active). However, when an 3.3 V, the LED can still be forward biased enough to glow. To ensure the LED extinguishes when ...
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Intel® i960® RM/RN I/O Processor Processor Power Supply Decoupling 10.0 Processor Power Supply Decoupling Processor power supply decoupling is critical for reliable operation. With the 3.3 V ready system, two areas of concern are described in • High frequency decoupling, ...
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Figure 10-23. High-Frequency Capacitor Values and Layout 10.2 Bulk Decoupling Capacitance Bulk, or low-frequency decoupling is needed on the separate power plane “island” necessary to place capacitance on the processor “island.” For bulk decoupling, place two 47 mF ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor Based Reference Design ® 11.0 Intel 80960RM/RN Processor Based Reference Design See Appendix A through RM/RN I/O processor 42 Appendix D for schematics and bill of material. OrCAD libraries for the ...
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Debug Connector Recommendations This section describes debug hardware and connectors developed for the This includes sockets, headers, logic analyzer interposer, Mictor* signal cross reference lists and JTAG emulator debug connector/pin assignments. 12.1 PBGA Sockets and Headers Figure 12-24 and ...
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Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-25. 540L PBGA Socket .812 inch .667 inch .312 inch .062 inch 44 .340 inch .05 inch Chamfer .062 inch 1.674 inch Top View .125 inch .193 inch .050 inch Side ...
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Logic Analyzer Connectivity The Mictor connector is the common connector used by the analysis connectivity. The Cyclone evaluation board developed for the 80960RM/RN integrates five Mictor connectors to route the appropriate signals for logic analysis and probing. See Table ...
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Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Figure 12-26. Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View Mictor* Connectors 1 38 1.91 inch Other brands and names are the property of their respective owners. Figure ...
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Figure 12-28. Flex Tape Interposer Application (Add-In Card) 312 mm Pin #1 PCI Connector Figure 12-29. Flex Tape Interposer (Top View) Figure 12-30. Flex Tape Interposer (Side View) Design Guide Intel® i960® RM/RN I/O Processor Debug Connector Recommendations Flex Tape ...
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Intel® i960® RM/RN I/O Processor Debug Connector Recommendations 12.3 JTAG Connector and Test Interface ® ® 12.3.1 Intel i960 The JTAG emulator for the i960 non-intrusive means of debugging. The JTAG emulator is connected to the processor by means of ...
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Figure 12-17 describes the interconnections required between the target debug interface connector and the pins/balls of the i960 RM/RN I/O processor family. ® Table 12-17. i960 RM/RN I/O Processor Debug Connector Wiring i960 Header Pin ...
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Intel® i960® RM/RN I/O Processor Debug Connector Recommendations 12.3.3 Connecting The Emulator To The Target The emulation software uses the first Test Access Port (TAP) on the PC-1149.1/100F boundary-scan controller card to control the i960 RM/RN I/O processor. A cable ...
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Table 12-19. i960 RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx) PCMCIA-1149.1 Signal Name TRST# GND TDO1 GND TDI1 GND TMS1 GND TCK1 (see note) GND PIO_0 GND PIO_1 GND PIO_2 (see note) - NOTE: Connected to target through ...
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Intel® i960® RM/RN I/O Processor Design for Manufacturability 13.0 Design for Manufacturability The RM/RN I/O processor packaging is explained extensively in the Intel 52 is offered in a high-thermal BGA (H-PBGA) package. PBGA ® Packaging Databook (Order Number 240800). Design ...
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Thermal Solutions In general, three factors affect the thermal performance of the BGA: package and board materials, package geometry and use environment. The H-PBGA package utilizes a heat spreader or slug across the top of the package to dissipate ...
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Intel® i960® RM/RN I/O Processor Thermal Solutions 14.2 3-Dimensional View: Processor with Heat Sink Attached To assist the board designer in component placement, hole placement and dimensions, Figure 14-33 and Figure 14-34 requiring a Passive Heat Sink. Figure 14-32. Conceptual ...
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PCB Heatsink Hole Dimensions Figure 14-33. Hole Dimensions for Passive Heatsink 2.98 mm REF 45 mm 34.798 mm 5.10 mm Board Pin Spring Board NOTES: The sides of the H-PBGA package are electrically conductive; traces run out to the ...
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Intel® i960® RM/RN I/O Processor Thermal Solutions Figure 14-34. Board Level Keep Out Areas 45 mm Trace and Component Keep Out Area = 3. Trace Keep-Out Areas Pin Keep-Out Area = 3.81 mm (Top and Bottom View) Clip ...
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Clearances of PCI Board and Components Figure 14-35. Clearances of PCI Board and Components 312 mm PCI Connector Design Guide Heat sink mounted on the package Heat sink mounted on the processor Add-in Card Motherboard Intel® i960® RM/RN I/O ...
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Intel® i960® RM/RN I/O Processor Thermal Solutions 14.5 Heat Sink Information Table 14-21 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or ...
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Shipping Tray Vendor Table 14-24. Shipping Tray Vendor Company 3M 14.5.5 Logic Analyzer Interposer Vendor Table 14-25. Logic Analyzer Interposer Vendor Company Packard-Hughes Interconnect 17150 Von Karman Ave Irvine, CA 92614-0968 14.5.6 JTAG Emulator Vendor Table 14-26. JTAG Emulator ...
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Intel® i960® RM/RN I/O Processor References 15.0 References 15.1 Related Documents Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. To obtain Intel literature: call 1-800-548-4725 or visit Intel’s website at http://www.intel.com Table 15-27. Related ...
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Intel i960 Schematics Schematics in this document supersede schematics in Document #AZ1-00886. Design Guide ® Intel RM I/O Processor Intel® i960® RM/RN I/O Processor ® i960 RM I/O Processor Schematics A 61 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-36. Decoupling and 3.3 V Power Schematic 62 Design Guide ...
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Figure 15-37. Primary PCI Interface Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics 63 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-38. Memory Controller Schematic 64 Design Guide ...
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Figure 15-39. Flash ROM, UART and LEDs Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics 65 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-40. Logic Analyzer I/F Schematic 66 Design Guide ...
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Figure 15-41. SDRAM 168-Pin DIMM Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics 67 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-42. Secondary PCI/80960 Core Schematic 68 Design Guide ...
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Figure 15-43. Secondary PCI Bus 1/2 Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics 69 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics Figure 15-44. Secondary PCI Bus 3/4 Schematic 70 Design Guide ...
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Figure 15-45. Battery Monitor Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RM I/O Processor Schematics 71 ...
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Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Intel IQ80960RM Board Bill of MaterialB This appendix identifies all components on the IQ80960RM Evaluation Platform ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet 1 of ...
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Table B-1. Intel IQ80960RM Bill of Materials (Sheet Item Qty Location C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, ...
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Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM Board Bill of Material ® Table B-1. Intel IQ80960RM Bill of Materials (Sheet Item Qty Location 30 1 R37 31 1 R47 32 1 R57 33 1 R19 34 ...
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Table B-1. Intel IQ80960RM Bill of Materials (Sheet Item Qty Location BT1, BT2, BT3, BT4 BT5, BT6, BT7, BT8 65 1 U15 66 3 C84 C60, C75 C78 C89, C90 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics ® ® Intel i960 Schematics Schematics in this document supersede schematics in Document #AZ1-00886 I/O Processor C Design Guide ...
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Figure 15-46. Decoupling and 3.3 V Power Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 77 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-47. Primary PCI Interface Schematic 78 Design Guide ...
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Figure 15-48. Memory Controller Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 79 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-49. Flash ROM, UART and LEDs Schematic 80 Design Guide ...
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Figure 15-50. Logic Analyzer I/F Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 81 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-51. SDRAM 168-Pin DIMM Schematic 82 Design Guide ...
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Figure 15-52. Secondary PCI/80960 Core Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 83 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-53. Secondary PCI Bus 1/2 Schematic 84 Design Guide ...
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Figure 15-54. Secondary PCI Bus 3/4 Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 85 ...
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Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics Figure 15-55. SPCI Pull-Ups Schematic 86 Design Guide ...
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Figure 15-56. Battery/Monitor Schematic Design Guide Intel® i960® RM/RN I/O Processor ® ® Intel i960 RN I/O Processor Schematics 87 ...
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Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Intel IQ80960RN Board Bill of MaterialD This appendix identifies all components on the IQ80960RN Evaluation Platform ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet 1 of ...
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Table D-1. Intel IQ80960RN Bill of Materials (Sheet Item Qty Location C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, ...
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Intel® i960® RM/RN I/O Processor ® Intel IQ80960RN Board Bill of Material ® Table D-1. Intel IQ80960RN Bill of Materials (Sheet Item Qty Location 33 1 R19 34 1 R29 35 1 R17 36 2 R48, R49 ...
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Table D-1. Intel IQ80960RN Bill of Materials (Sheet Item Qty Location 65 1 C84 C60, C75 C78 C89, C90 C91, C93 68 1 C63 C57, C76 C88, C92 70 1 ...
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Intel® i960® RM/RN I/O Processor ® Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations ® Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations MODULE BATT //TITLE SDRAM Battery Backup Enable //PATTERN101-1809-01 //REVISION //AUTHORJ. Neumann //COMPANYCyclone Microsystems Inc. //DATE 10/30/97 //CHIP PALLV16V8Z-20JI // ...
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Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-1 details the ballout for the 80960RM processor. Table F-1. 540-Lead H-PBGA Pinout — Intel Ball # Signal P_AD29 A7 ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-1. 540-Lead H-PBGA Pinout — Intel Ball # Signal C30 V C31 V C32 ...
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Table F-1. 540-Lead H-PBGA Pinout — Intel Ball # Signal L1 P_DEVSEL# L2 P_TRDY# L3 P_IRDY P_FRAME# L28 SDQM4 L29 SDQM0 L30 SCAS# L31 V L32 SWE# M1 P_SERR P_PERR# M4 P_LOCK# M5 P_STOP# ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-1. 540-Lead H-PBGA Pinout — Intel Ball # Signal AB30 DQ22 AB31 DQ53 AB32 DQ21 AC1 P_AD46/ N/C AC2 P_AD47/ N/C AC3 P_AD48/ N/C AC4 V ...
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Table F-1. 540-Lead H-PBGA Pinout — Intel Ball # Signal AK1 V AK2 V AK3 V AK4 V AK5 S_AD37/ N/C AK6 S_AD40/ N/C AK7 S_AD45/ N/C AK8 S_AD48/ N/C AK9 S_AD53/ N/C AK10 S_AD56/ N/C AK11 S_AD61/ N/C AK12 ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-2 details the ballout for the 80960RN processor. Table F-2. 540-Lead H-PBGA Pinout — Intel Ball # Signal ...
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Table F-2. 540-Lead H-PBGA Pinout — Intel Ball # Signal D16 V D17 V D18 RAD14 D19 V D20 ROE# D21 V D22 DQ00 D23 V D24 DQ04 D25 V D26 V CCPLL D27 V D28 V D29 V D30 ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-2. 540-Lead H-PBGA Pinout — Intel Ball # Signal M31 SDQM5 M32 SDQM1 N1 P_AD14 N2 P_AD15 N3 P_PAR P_C/BE1# N28 SA02 N29 ...
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Table F-2. 540-Lead H-PBGA Pinout — Intel Ball # Signal AD28 DQ58 AD29 V AD30 DQ26 AD31 DQ57 AD32 DQ25 AE1 P_AD38 AE2 P_AD39 AE3 P_AD40 AE4 V AE5 P_AD41 AE28 DQ60 AE29 DQ28 AE30 DQ59 AE31 V AE32 DQ27 ...
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Intel® i960® RM/RN I/O Processor ® Intel 80960RM/RN Processor PBGA Signal Ball Map Table F-2. 540-Lead H-PBGA Pinout — Intel Ball # Signal AK19 S_PAR AK20 S_LOCK# AK21 S_FRAME# AK22 S_AD17 AK23 S_AD22 AK24 S_AD24 AK25 S_AD29 AK26 S_RST# AK27 ...