AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 208

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
15.6.9
15.6.9.1
32072G–11/2011
Internal signal from PM
Slow Clock Mode
NBS0, NBS1,
A[AD_MSB:2]
Asynchronous Page Mode
A0, A1
CLK_SMC
Protocol and timings in page mode
Clock Mode
NWE
NCS
The SMC supports asynchronous burst reads in page mode, providing that the Page Mode
Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be con-
figured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
the SMC enables the user to define different read timings for the first access within one page,
and next accesses within the page.
Table 15-6.
Notes:
Figure 15-33 on page 209
SLOW CLOCK MODE WRITE
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored.
1
Page Address and Data Address within a Page
A[23:2]
A[23:3]
A[23:4]
A[23:5]
Page Address
1
shows the NRD and NCS timings in page mode access.
sa
) as shown in
(1)
IDLE STATE
Table 15-6 on page
Figure 15-33 on page
Reload Configuration
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
Wait State
2
pa
NORMAL MODE WRITE
) takes longer than the subse-
208.
209. When in page mode,
3
(2)
2
208