AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 518

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.6
24.7.6.1
24.7.7
32072G–11/2011
Receive Compare Modes
Data Framing Format
Compare functions
and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
Figure 24-12. Receive Compare Modes
Compare 0 can be one start event of the receiver. In this case, the receiver compares at each
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
The data framing format of both the transmitter and the receiver are programmable through the
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
Table 24-3.
• the event that starts the data transfer (RCMR.START and TCMR.START)
• the delay in number of bit periods between the start event and the first data bit
• the length of the data (RFMR.DATLEN and TFMR.DATLEN)
• the number of data to be transferred for each start event (RFMR.DATNB and
• the length of synchronization transferred for each start event (RFMR.FSLENHI,
• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)
Transmitter
(RCMR.STTDLY and TCMR.STTDLY)
TFMR.DATLEN)
RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)
TCMR
TCMR
TCMR
RX_CLOCK
RX_DATA
Data Framing Format Registers
(Input)
Receiver
RCMR
RCMR
RCMR
CMP0
(4 in This Example)
{FSLENHI,FSLEN}
CMP1
Up to 256 Bits
Bit/Field
PERIOD
STTDLY
START
CMP2
CMP3
Start
Up to 512
Up to 255
Length
STTDLY
Ignored
Frame size
Start selection
Size of transmit start delay
B0
Comment
DATLEN
B1
B2
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