AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 331

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AT32UC3A364

Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A364

Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32072G–11/2011
Figure 19-8. Multi-Block with Linked List Address for Source and Destination
If the user needs to execute a DMA transfer where the source and destination address are con-
tiguous but the amount of data to be transferred is greater than the maximum block size
CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in
Figure 19-9 on page
transfer continues until the DMACA determines that the CTLx and LLPx registers at the
end of a block transfer match that described in Row 1 or Row 5 of
326. The DMACA then knows that the previous block transferred was the last block in
the DMA transfer. The DMA transfer might look like that shown in
331.
Source Layer
Address of
SAR(2)
SAR(1)
SAR(0)
332.
Source Blocks
Block 1
Block 2
Block 0
DAR(2)
DAR(1)
DAR(0)
Destination Blocks
Block 1
Block 2
Block 0
Destination Layer
Figure 19-8 on page
Table 19-1 on page
Address of
331

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