AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 193
AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 193 of 1012
- Download datasheet (16Mb)
32072G–11/2011
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
time
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page
an early read wait state, the write operation could not complete properly.
(NWEHOLD = 0), the feedback of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See
NBS0, NBS1,
A[AD_MSB:2]
(Figure 15-16 on page
A0, A1
CLK_SMC
D[15:0]
NWE
NRD
194). The write operation must end with a NCS rising edge. Without
Write cycle
193).
No hold
Early Read
Wait state
Figure 15-18 on page
No setup
Read cycle
195.
193
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