AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 486
AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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23.8.8
23.8.8.1
Figure 23-14. A Write Transfer with 10-bit Addressing
23.8.8.2
Figure 23-15. A Read Transfer with 10-bit Addressing
23.8.9
32072G–11/2011
S
1
SLAVE ADDRESS
1
Ten Bit Addressing
SMBus Mode
1
1st 7 bits
Master Transmitter
Master Receiver
1
0
S
X
1
X
SLAVE ADDRESS
1
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In
white boxes are driven by the slave.
To perform a master transmitter transfer:
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
RW A1
SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
0
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,
2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput on
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
1
Figure 23-14
1st 7 bits
the bus. These timeout values must be written into SMBTR.
Address (ARA) and Host Header (HH) Address.
1
desired address and NBYTES value.
NBYTES=0 and the desired address.
desired address and NBYTES value.
0
X
SLAVE ADDRESS
X
2nd byte
and
RW A1
0
Figure
SLAVE ADDRESS
23-15, the grey boxes represent signals driven by the master, the
A2
2nd byte
Sr
1
SLAVE ADDRESS
1
1
1st 7 bits
1
A2
0
DATA
X
X
A
RW A3
1
DATA
DATA
A
AA
P
DATA
A
P
486
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