AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 234
AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 234 of 1012
- Download datasheet (16Mb)
16.8.3
Register Name:
Access Type:
Offset:
Reset Value:
• TXSR: Exit Self Refresh to Active Delay
• TRAS: Active to Precharge Delay
• TRCD: Row to Column Delay
• TRP: Row Precharge Delay
• TRC: Row Cycle Delay
• TWR: Write Recovery Delay
• DBW: Data Bus Width
32072G–11/2011
DBW
31
23
15
7
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is five cycles.
This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0
and 15.
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
Reset value is 16 bits.
0: Reserved.
1: Data bus width is 16 bits.
Configuration Register
30
22
14
6
CR
Read/Write
0x08
0x852372C0
TRCD
TXSR
TRC
CAS
29
21
13
5
NB
28
20
12
4
27
19
11
3
NR
26
18
10
2
TRAS
TWR
TRP
25
17
9
1
NC
24
16
8
0
234
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