AT83C5134 Atmel Corporation, AT83C5134 Datasheet - Page 120

• Manufacturer Part Number: AT83C5134
• Manufacturer: Atmel Corporation

Specifications of AT83C5134

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 8
• Watchdog: Yes

21.11 USB Registers
120
AT83C5134/35/36
Table 21-3.
Reset Value = 00h
Bit Number
USBE
7
7
6
5
4
3
2
1
0
SUSPCLK
Bit Mnemonic
USBCON Register
USBCON (S:BCh)
USB Global Control Register
SDRMWUP
SUSPCLK
RMWUPE
DETACH
FADDEN
UPRSM
CONFG
6
USBE
SDRMWUP
5
Description
USB Enable
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB
transceiver an to disable the USB controller clock inputs.
Suspend USB Clock
Set this bit to disable the 48 MHz clock input (Resume Detection is still active).
Clear this bit to enable the 48 MHz clock input.
Send Remote Wake Up
Set this bit to force an external interrupt on the USB controller for Remote Wake
UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM
below.
This bit is cleared by software.
Detach Command
Set this bit to simulate a Detach on the USB line. The V
state.
Clear this bit to maintain V
Upstream Resume (read only)
This bit is set by hardware when SDRMWUP has been set and if RMWUPE is
enabled.
This bit is cleared by hardware after the upstream resume has been sent.
Remote Wake-Up Enable
Set this bit to enabled request an upstream resume signaling to the host.
Clear this bit otherwise.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP
feature for the device.
Configured
This bit will be set by the device firmware after a SET_CONFIGURATION request
with a non-zero value has been correctly processed.
It will be cleared by the device firmware when a SET_CONFIGURATION request
with a zero value is received. It is cleared by hardware on hardware reset or when
an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times:
typically 2.7 µs).
Function Address Enable
This bit will be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It will not be cleared afterwards by the device firmware. It is cleared by hardware
on hardware reset or when an USB reset is received (see above). When this bit is
cleared, the default function address is used (0).
DETACH
4
UPRSM
REF
3
at high level.
RMWUPE
2
REF
CONFG
pin is then in a floating
1
7683C–USB–11/07
FADDEN
0