AT83C5134 Atmel Corporation, AT83C5134 Datasheet - Page 26
AT83C5134
Manufacturer Part Number
AT83C5134
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT83C5134.pdf
(166 pages)
Specifications of AT83C5134
Max. Operating Frequency
32 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
512
Operating Voltage (vcc)
2.7 to 3.6
Timers
4
Mask Rom (kbytes)
8
Watchdog
Yes
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8.1.2
26
AT83C5134/35/36
External Bus Cycles
Table 8-1.
This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see
Figure 8-3) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri-
ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2
mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and
do not provide precise timing information.
Figure 8-3.
Signal
Name
AD7:0
PSEN
A15:8
ALE
CPU Clock
PSEN
ALE
Type
P0
P2
I/O
O
O
O
External Data Memory Interface Signals
External Code Fetch Waveforms
D7:0
PCH
Description
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read (MOVC
instruction).
PCL
PCH
D7:0
PCL
PCH
D7:0
7683C–USB–11/07
Alternate
Function
P2.7:0
P0.7:0
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