AT83C5134 Atmel Corporation, AT83C5134 Datasheet - Page 77

• Manufacturer Part Number: AT83C5134
• Manufacturer: Atmel Corporation

Specifications of AT83C5134

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 8
• Watchdog: Yes

19.3
19.3.1
7683C–USB–11/07
Functional Description
Operating Modes
Figure 19-2
Figure 19-2. SPI Module Block Diagram
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI module is made through one register:
Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex trans-
mission with both data out and data in synchronized with the same clock (Figure 19-3).
• The Serial Peripheral CONtrol register (SPCON)
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
SPI Interrupt Request
shows a detailed structure of the SPI module.
Clock
Divider
FCLK PERIPH
SPR2
/128
/16
/32
/64
SPEN
/8
/4
Clock
Select
SSDIS
MSTR
SPIF
Receive Data Register
CPOL
WCOL
7
Shift Register
Internal Bus
6
SPI
Control
CPHA
5
SSERR
4
3
SPR1
2
Clock
Logic
SPCON
1
SPDAT
MODF
AT83C5134/35/36
0
SPR0
-
M
Pin
Control
Logic
S
-
-
SPSTA
-
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
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