AT89C51RC2 Atmel Corporation, AT89C51RC2 Datasheet - Page 89
AT89C51RC2
Manufacturer Part Number
AT89C51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
1.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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4180E–8051–10/06
Table 67. Default Values
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 68. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 69.
Mnemonic
Number
Bit
SBV
HSB
BSB
SSB
1-0
7
-
7
6
5
4
3
2
Mnemonic Description
Definition
Software Boot Vector
Hardware security Byte
Boot Status Byte
Software Security Byte
Copy of the Manufacturer Code
Copy of the Device ID #1: Family Code
Copy of the Device ID #2: memories
size and type
Copy of the Device ID #3: name and
revision
LB1-0
Bit
6
-
-
-
-
-
-
-
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
see Table 69
5
-
4
-
3
-
Default value
101x 1011b
AT89C51RB2/RC2
0FFh
FCh
D7h
FBh
EFh
FFh
58h
F7h
FFh
2
-
Description
ATMEL
C51 X2, Electrically Erasable
AT89C51RB2/RC2 32KB
AT89C51RB2/RC2 16 KB
AT89C51RB2/RC2 32KB,
Revision 0
AT89C51RB2/RC2 16 KB,
Revision 0
LB1
1
LB0
0
89