AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 110

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 17-1.
Notes:
110
SCON Address = 98H
Bit Addressable
Bit
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
(SMOD0 = 0/1)
1. SMOD0 is located at PCON.6.
2. f
AT89LP51RD2/ED2/ID2 Preliminary
SM0/FE
SYS
Function
Framing Error Bit
This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames and must be
cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set regardless of the state of
SMOD0.
Serial Port Mode Bit 0
Refer to SM1 for serial port mode selection. SMOD0 must = 0 to access bit SM0.
Serial Port Mode Bit 1
Multiprocessor Communications Enable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 determines the idle state of the shift clock such that the clock is the inverse of SM2, i.e. when SM2 = 0
the clock idles high and when SM2 = 1 the clock idles low.
Serial Reception Enable
Set by software to enable reception. Clear by software to disable reception.
Transmitter Bit 8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Mode 0, setting TB8
enables Timer 1 as the shift clock generator.
Receiver Bit 8
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode
0, RB8 is not used.
Transmit Interrupt Flag
Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any
serial transmission. Must be cleared by software.
Receive Interrupt Flag
Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any
serial reception (except see SM2). Must be cleared by software.
7
SCON – Serial Port Control Register
= system frequency. The baud rate depends on SMOD1 (PCON.7).
SM0
0
0
1
1
(1)
SM1
6
SM1
0
1
0
1
SM2
5
Mode
0
1
2
3
REN
4
Description
shift register
8-bit UART
9-bit UART
9-bit UART
TB8
3
variable (Timer 1 or Timer 2)
variable (Timer 1 or Timer 2)
f
Baud Rate (Compat.)
SYS
/3 or f
f
SYS
/32 or f
SYS
RB8
2
/6 or Timer 1
SYS
/16
Reset Value = 0000 0000B
(2)
T1
1
variable (Timer 1 or Timer 2)
variable (Timer 1 or Timer 2)
f
SYS
Baud Rate (Fast)
/2 or f
f
SYS
/32 or f
SYS
3714A–MICRO–7/11
RI
0
/4 or Timer 1
SYS
/16
(2)