AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 109

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

17. Serial Interface (UART)
3714A–MICRO–7/11
The serial interface on the AT89LP51RD2/ED2/ID2 implements a Universal Asynchronous
Receiver/Transmitter (UART). The UART has the following features:
The serial interface is full-duplex, which means it can transmit and receive simultaneously. It is
also receive-buffered, which means it can begin receiving a second byte before a previously
received byte has been read from the receive register. (However, if the first byte still has not
been read when reception of the second byte is complete, one of the bytes will be lost.) The
serial port receive and transmit registers are both accessed at the Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically
separate receive register. The serial port can operate in the following four modes.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initi-
ated in the other modes by the incoming start bit if REN = 1.
• Full-duplex Operation
• 8 or 9 Data Bits
• Framing Error Detection
• Multiprocessor Communication Mode with Automatic Address Recognition
• Baud Rate Generator Using Timer 1, Timer 2 or dedicated Internal Baud Rate Generator
• Interrupt on Receive Buffer Full or Transmission Complete
• Synchronous SPI or TWI Master Emulation
• Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data
• Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
• Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
• Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
bits are transmitted/received, with the LSB first. The baud rate is programmable to 1/6 or 1/3
the system frequency in Compatibility mode, 1/4 or 1/2 the system frequency in Fast mode,
or variable based on Time 1.
8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in the Special
Function Register SCON. The baud rate is variable based on Timer 1 or Timer 2.
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th
data bit (TB8 in SCON) can be assigned the value of “0” or “1”. For example, the parity bit
(P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in the
Special Function Register SCON, while the stop bit is ignored. The baud rate is
programmable to either 1/16 or 1/32 the system frequency.
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the
same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 or
Timer 2 in Mode 3.
AT89LP51RD2/ED2/ID2 Preliminary
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