AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 58
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AT89LP51RD2
Manufacturer Part Number
AT89LP51RD2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RD2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP51RD2-20AAU
Manufacturer:
INFINEON
Quantity:
450
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8.2
8.2.1
58
Power-down Mode
AT89LP51RD2/ED2/ID2 Preliminary
Interrupt Recovery from Power-down
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
Two external interrupt sources may be configured to terminate Power-down mode: external
interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that inter-
rupt must be enabled by setting EX0 or EX1 in IE and must be configured for level-sensitive
operation by clearing IT0 or IT1.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is one, the wake-up period is internally timed as shown in
the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see
The interrupt pin need not remain low for the entire time-out period.
Figure 8-1.
When PWDEX = “0”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in
2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Internal
XTAL1
Clock
PWD
INT1
Interrupt Recovery from Power-down (PWDEX = 1)
t SUT
Table 7-1 on page
3714A–MICRO–7/11
Figure
DD
has been
Figure 8-
8-1. At
54).
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