AT90PWM316 Atmel Corporation, AT90PWM316 Datasheet - Page 166

• Manufacturer Part Number: AT90PWM316
• Manufacturer: Atmel Corporation

Specifications of AT90PWM316

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.25.8
16.25.9
16.25.10 PSC 2 Configuration Register – PCNF2
7710F–AVR–09/11
PSC 0 Configuration Register – PCNF0
PSC 1 Configuration Register – PCNF1
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSC counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width
modulation.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers.
The PSC n Configuration Register is used to configure the running mode of the PSC.
• Bit 7 - PFIFTYn: PSC n Fifty
Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRn-
SBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of
OCRnRBH/L. This feature is useful to perform fifty percent waveforms.
• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and
the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The
update of the PSC internal registers will be done at the end of the PSC cycle if the Output Com-
pare Register RB has been the last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCKn: PSC n Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2
and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles.
The update of the PSC internal registers will be done if the LOCK bit is released to zero.
• Bit 4:3 – PMODEn1: 0: PSC n Mode
Select the mode of PSC.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PFIFTY0
PFIFTY1
PFIFTY2
R/W
R/W
R/W
7
0
7
0
7
0
PALOCK0
PALOCK1
PALOCK2
R/W
R/W
R/W
6
6
6
0
0
0
PLOCK0
PLOCK1
PLOCK2
R/W
R/W
R/W
5
0
5
0
5
0
PMODE01
PMODE11
PMODE21
R/W
R/W
R/W
4
0
4
0
4
0
PMODE00
PMODE10
PMODE20
R/W
R/W
R/W
3
0
3
0
3
0
POP0
POP1
POP2
AT90PWM216/316
R/W
R/W
R/W
2
0
2
0
2
0
PCLKSEL0
PCLKSEL1
PCLKSEL2
R/W
R/W
R/W
1
0
1
0
1
0
POME2
R/W
R/W
R/W
0
0
0
0
0
0
-
-
PCNF0
PCNF1
PCNF2
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