ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 49

• Manufacturer Part Number: ATmega1280R212
• Manufacturer: Atmel Corporation

Specifications of ATmega1280R212

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 86
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

10.10 Clock Output Buffer
10.11 Timer/Counter Oscillator
10.12 System Clock Prescaler
2549N–AVR–05/11
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
details.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter-
nal clock source. See
Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to
logic one. See
on selecting external clock as input instead of a 32kHz crystal.
The ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system clock can
be divided by setting the
used to decrease the system clock frequency and the power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to
zero.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
“Asynchronous Operation of Timer/Counter2” on page 184
Figure 10-2 on page 43
“CLKPR – Clock Prescale Register” on page
ATmega640/1280/1281/2560/2561
Table 10-15 on page
for crystal connection.
51.
I/O
“System Clock Prescaler”
, clk
ADC
50. This feature can be
for further description
, clk
CPU
, and clk
FLASH
for
49