ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 156
ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 156 of 367
- Download datasheet (7Mb)
14.16.10 PSC Interrupt Mask Register – PIM
156
Atmel ATmega16/32/64/M1/C1
Table 14-12. Input Mode Operation
Bit
Read/Write
Initial Value
• Bit 7:4 – not use
not use.
• Bit 3 – PEVE2 : PSC External Event 2 Interrupt Enable
When this bit is set, an external event which can generates a a fault on module 2 generates
also an interrupt.
• Bit 2 – PEVE1 : PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also
an interrupt.
• Bit 1 – PEVE0 : PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also
an interrupt.
• Bit 0 – PEOPE : PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
PRFMn2:0
000b
001b
010b
011b
10x
11xb
R
7
0
-
Description
No action, PSC Input is ignored
Disactivate module n Outputs A
Disactivate module n Output B
Disactivate module n Output A & B
Disactivate all PSC Output
Halt PSC and Wait for Software Action
R
6
0
-
R
5
0
-
R
4
0
-
PEVE2
R/W
3
0
PEVE1
R/W
2
0
PEVE0
R/W
1
0
PEOPE
R/W
0
0
7647G–AVR–09/11
PIM
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