ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 213
ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 213 of 367
- Download datasheet (7Mb)
17.5.4
17.5.5
17.5.5.1
7647G–AVR–09/11
1) LBUSY
2) LBUSY
3) LBUSY
LIN bus
Configuration
Busy Signal
Busy Signal in LIN Mode
LCMD=Tx Header
BREAK
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the con-
troller in the following configuration
Table 17-3.
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this
mode, the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same
scheme is available in UART mode.
Figure 17-6. Listening Mode
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by
hardware. It signals that the controller is busy with LIN or UART communication.
Figure 17-7. Busy Signal in LIN Mode
Node providing the master task
Mode
UART
Field
LIN
HEADER
LCONF[1..0]
SYNC
Configuration Table versus Mode
00
01
10
11
00
01
10
11
Node providing neither the master task, neither a slave task
Field
b
b
b
b
b
b
b
b
LISTEN
Rx LIN
Tx LIN
internal
internal
PROTECTED
IDENTIFIER
LIDOK
Field
FRAME SLOT
(Table
Atmel ATmega16/32/64/M1/C1
Listening mode, 8-bit data, no parity & 1 stop-bit
1
0
No CRC field detection or transmission
17-3):
LCMD=Tx or Rx Response
LIN standard configuration (default)
8-bit data, even parity & 1 stop-bit
8-bit data, odd parity & 1 stop-bit
DATA-0
8-bit data, no parity & 1 stop-bit
Frame_Time_Out disable
Field
Listening mode
Configuration
Node providing a slave task
RESPONSE
RXLIN
TXLIN
DATA-n
Field
LTXOK or LRXOK
CHECKSUM
Field
213
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