ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 200
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21.8
21.9
7799D–AVR–11/10
Suspend, Wake-up and Resume
Detach
UADD contains the default address 00h after a power-up or an USB reset.
ADDEN is cleared by hardware:
When this bit is cleared, the default device address 00h is used.
After the USB line has been inactive for a period of 3 ms (J state), the controller set the SUSPI
flag and triggers the corresponding interrupt if enabled. The firmware may then set the FRZCLK
bit.
The CPU can also, depending on software architecture, disable the PLL and/or enter in the idle
mode to reduce the power consumption (especially in a bus powered application).
There are two ways to recover from the Suspend mode:
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKE-
UPI interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the
WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared
by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared
by hardware.
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit (the line
discharge time must be taken in account).
Figure 21-3. Detach a device in Full-speed:
• after a power-up reset,
• when an USB reset is received,
• or when the macro is disabled (USBE cleared)
1. Clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.
2. If the CPU is in idle mode, enable the WAKEUPI interrupt (WAKEUPE set). Then, as
• When the USB device controller is in full-speed mode, setting DETACH will disconnect the
pull-up on the D+. Then, clearing DETACH will connect the pull-up on the D+.
soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.
The firmware shall then clear the FRZCLK bit to restart the transfer.
UVREF
EN=1
D +
D -
Detach, then
Attach
ATmega8U2/16U2/32U2
UVREF
EN=1
D +
D -
200
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