ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 43

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.2.2
10.2.3
8127E–AVR–11/11
Toggling the Pin
Break-Before-Make Switching
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor
off, PUExn has to be written logic zero.
Table 10-1
Table 10-1.
Port pins are tri-stated when a reset condition becomes active, even when no clocks are
running.
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an imme-
diate tri-state period lasting one system clock cycle, as indicated in
the system clock is 4 MHz and the DDRxn is written to make an output, an immediate tri-state
period of 250 ns is introduced before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make mode applies to the entire port and it is activated by the
BBMx bit. For more details, see
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
DDxn
0
0
1
1
1
1
PORTxn
summarizes the control signals for the pin value.
Port Pin Configurations
X
X
0
0
1
1
PUExn
0
1
0
1
0
1
I/O
Input
Input
Output
Output
Output
Output
“PORTCR – Port Control Register” on page
Pull-up
No
Yes
No
Yes
No
Yes
Sources current if pulled low externally
Output high (source)
Output high (source) and internal pull-up active
Comment
Tri-state (hi-Z)
Output low (sink)
NOT RECOMMENDED.
Output low (sink) and internal pull-up active.
Sources current through the internal pull-up
resistor and consumes power constantly
Figure
ATtiny4/5/9/10
10-3. For example, if
51.
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