ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 96

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ATtiny5

Manufacturer Part Number
ATtiny5
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny5

Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
8
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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13.12.4
13.12.5
96
ATtiny4/5/9/10
ADCL
DIDR0
ADC Data Register
Digital Input Disable Register 0
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 13-4.
When an ADC conversion is complete, the result is found in the ADC register.
• Bits 7:0 – ADC7:0: ADC Conversion Result
These bits represent the result from the conversion.
• Bits 7:4 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bits 3:0 – ADC3D..ADC0D: ADC3..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Bit
0x19
Read/Write
Initial Value
Bit
0x17
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC7
ADC Auto Trigger Source Selections
R
7
0
R
7
0
ADC6
R
6
0
R
6
0
ADTS1
0
0
1
1
0
0
1
1
ADC5
R
5
0
R
5
0
ADC4
R
R
4
0
4
0
ADTS0
0
1
0
1
0
1
0
1
ADC3D
ADC3
R/W
R
3
0
3
0
ADC2D
ADC2
R/W
R
2
0
2
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Flag 0
Timer/Counter 0 Compare Match A
Timer/Counter 0 Overflow
Timer/Counter 0 Compare Match B
Pin Change Interrupt 0 Request
Timer/Counter 0 Capture Event
ADC1D
ADC1
R/W
R
1
0
1
0
ADC0
ADC0D
R/W
R
0
0
0
0
ADCL
DIDR0
8127E–AVR–11/11
.

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