ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 38

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.10.1
3.10.2
3.11
32002F–03/2010
NMI latency
Maximum interrupt latency
Minimum interrupt latency
Note that the overall system latency from an interrupt request is signaled to the request is being
handled depends on a number of things in addition to the latency through the CPU. The latency
through the interrupt controller will affect interrupt latency for all peripheral interrupt requests and
the bus matrix, code and data memories will affect overall responsiveness.
The maximum CPU interrupt latency can be calculated as follows:
Table 3-7.
The minimum CPU interrupt latency of an interrupt request of level m will occur when the CPU is
in the process of stacking the registers and return address associated with an interrupt request
of level n, where n < m. If the level m interrupt request arrives just as the CPU is about to jump to
the autovector address for the interrupt of level n, the CPU will jump directly to the autovector
address of the latest arriving interrupt. In this case, the minimum interrupt latency is as follows:
Table 3-8.
Assuming that the interrupt request arrives when the CPU is in the process of executing program
code, the minimum interrupt latency can be calculated as follows:
Table 3-9.
Non-maskable interrupts (NMI) behave similarly to interrupts, except that they do not automati-
cally push register file registers on the stack. NMI can, similar to interrupts, abort long-running
instructions.
Source
Wait for the slowest instruction to complete
Stack register file registers, return address and status register, and jump to
autovector target
Wait for autovector target instruction to be fetched
TOTAL
Source
Jump to autovector target
Wait for autovector target instruction to be fetched
TOTAL
Source
Wait for the fastest instruction to complete
Stack register file registers, return address and status register, and jump to
autovector target
Wait for autovector target instruction to be fetched
TOTAL
Maximum interrupt latency
Minimum interrupt latency - higher priority interrupt preempts lower priority
interrupt
Minimum interrupt latency - interrupt received when executing program code
Delay
6
10
1
17
Delay
1
1
2
Delay
1
10
1
12
AVR32
38