ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 5

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ATUC64L4U

Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC64L4U

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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1.8
32002F–03/2010
AVR32UC CPU revisions
Figure 1-1.
Three revisions of the AVR32UC CPU currently exist:
Revision 2 of the AVR32UC CPU added the following instructions:
Revision 3 of the AVR32UC CPU added the following instructions:
• Revision 1 implementing revision 1 of the AVR32 architecture.
• Revision 2 implementing revision 2 of the AVR32 architecture, and with a faster divider.
• Revision 3 implementing revision 3 of the AVR32 architecture, and with optional floating-point
• movh Rd, imm
• {add, sub, and, or, eor}{cond4}, Rd, Rx, Ry
• ld.{sb, ub, sh, uh, w}{cond4} Rd, Rp[disp]
• st.{b, h, w}{cond4} Rp[disp], Rs
• rsub{cond4} Rd, imm
hardware.
Instruction memory controller
High Speed Bus master
Overview of AVR32UC.
system
OCD
AVR32UC CPU pipeline
MPU
master
Speed
High
Bus
Data memory controller
Bus slave
Speed
High
CPU Local
Power/
control
Reset
master
Bus
AVR32
5

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