ATxmega128D4 Atmel Corporation, ATxmega128D4 Datasheet - Page 60
ATxmega128D4
Manufacturer Part Number
ATxmega128D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128D4
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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6.6
6.7
8210B–AVR–04/10
PLL with 1-31x Multiplication Factor
DFLL 2 MHz and DFLL 32 MHz
The System Clock selection and prescaler registers are protected by the Configuration Change
Protection mechanism, employing a timed write procedure for changing the system clock and
prescaler settings. For details refer to
A built-in Phase Locked Loop (PLL) can be used to generate a high frequency system clock. The
PLL has a user selectable multiplication factor from 1 to 31. The output frequency, f
by the input frequency, f
imum and minimum input and output frequency for the PLL, refer to the device datasheet.
Four different reference clock sources can be chosen as input to the PLL:
To enable the PLL the following procedure must be followed:
1.Enable clock reference source.
2.Set the multiplication factor and select the clock reference for the PLL.
3.Wait until the clock reference source is stable.
4.Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The
PLL must be disabled before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stabile and the PLL has
locked.
If using PLL and DFLL the active reference cannot be disabled.
Two built-in Digital Frequency Locked Loops (DFLLs) can be used to improve the accuracy of
the 2 MHz and 32 MHz internal oscillators. The DFLL compares the oscillator frequency with a
more accurate reference clock to do automatic run-time calibration of the oscillator. The choices
for the reference clock sources are:
The DFLLs divide the reference clock by 32 to use a 1.024 kHz reference. The reference clock is
individually selected for each DFLL as shown on
• 2 MHz internal oscillator
• 32 MHz internal oscillator divided by 4
• 0.4 - 16 MHz Crystal Oscillator
• External clock
• 32.768 kHz Calibrated Internal Oscillator
• 32.768 kHz Crystal Oscillator connected to the TOSC pins
IN
multiplied with the multiplication factor, PLL_FAC. For details on max-
”Configuration Change Protection” on page
f
OUT
=
f
IN
⋅
Figure 6-6 on page
PLL_FAC
61.
XMEGA D
12.
OUT
is given
60
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