ATxmega128D4 Atmel Corporation, ATxmega128D4 Datasheet - Page 61
ATxmega128D4
Manufacturer Part Number
ATxmega128D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128D4
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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6.8
8210B–AVR–04/10
External Clock Source Failure Monitor
Figure 6-6.
When the DFLL is enabled it will count each oscillator clock cycle, and for each reference clock
edge, the counter value is compared to the fixed ideal relationship between the reference clock
and the 1.024 kHz reference frequency. If the internal oscillator runs too fast or too slow, the
DFLL will decrement or increment the corresponding DFLL Calibration Register value by one to
adjust the oscillator frequency slightly. When the DFLL is enabled the DFLL Calibration Register
cannot be written from software.
The ideal counter value representing the number of oscillator clock cycles for each reference
clock cycle is loaded to the DFLL Oscillator Compare Register during reset. The register can
also be written from software to change the frequency the internal oscillator is calibrated to.
The DFLL will stop when entering a sleep-mode where the oscillators are stopped. After wake-
up the DFLL will continue with the calibration value found before entering sleep. For the DFLL
Calibration Register to be reloaded with the default value it has after reset, the DFLL must dis-
abled before entering sleep and enabled the again after leaving sleep.
The active reference cannot be disabled when the DFLL is enabled.
When the DFLL is disabled the DFLL calibration Register can be written from software for man-
ual run-time calibration of the oscillator.
For details on internal oscillator accuracy when the DFLL is enabled, refer to the device
datasheet.
To handle external clock source failures, there is a built-in monitor circuit monitoring the oscilla-
tor or clock used to derive the XOSC clock. The External Clock Source Failure Monitor is
disabled by default, and it must be enabled from software before it can be used. If an external
TOSC1
TOSC2
Figure 5-5. DFLL reference clock selection
32.768 kHz Crystal Osc.
32.768 kHz Int. Osc.
32 MHz Int. Osc.
2 MHz Int. Osc.
DFLL
DFLL
XMEGA D
61
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