RM9200 Atmel Corporation, RM9200 Datasheet - Page 132
RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 132 of 284
- Download datasheet (2Mb)
Debug Interface
5.4
5.4.1
5-10
ARM7TDMI core clock domains
Clock switch during debug
The ARM7TDMI clocks are described in Clocks on page 5-2.
This section describes:
•
•
When the ARM7TDMI processor enters debug state, it switches automatically from
MCLK to DCLK, it then asserts DBGACK in the HIGH phase of MCLK. The switch
between the two clocks occurs on the next falling edge of MCLK. This is shown in
Figure 5-4.
The core is forced to use DCLK as the primary clock until debugging is complete. On
exit from debug, the core must be allowed to synchronize back to MCLK. This must be
done by the debugger in the following sequence:
1.
2.
The core now automatically resynchronizes back to MCLK and starts fetching
instructions from memory at MCLK speed.
See Exit from debug state on page B-26.
Clock switch during debug on page 5-10
Clock switch during test on page 5-11.
The final instruction of the debug sequence is shifted into the data bus scan chain
and clocked in by asserting DCLK.
RESTART is clocked into the TAP instruction register.
DBGACK
Copyright © 1994-2001. All rights reserved.
MCLK
DCLK
ECLK
Figure 5-4 Clock switching on entry to debug state
Multiplexer
switching point
ARM DDI 0029G
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