RM9200 Atmel Corporation, RM9200 Datasheet - Page 99
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RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 99 of 284
- Download datasheet (2Mb)
3.7
3.7.1
3.7.2
ARM DDI 0029G
Stretching access times
Modulating MCLK
Use of nWAIT to control bus cycles
The ARM7TDMI processor does not contain any dynamic logic that relies on regular
clocking to maintain the internal state. Therefore, there is no limit upon the maximum
period for which MCLK can be stretched, or nWAIT held LOW. There are two
methods available to stretch access times as described in:
•
•
If you wish to use an Embedded Trace Macrocell (ETM) to obtain instruction and data
trace information on a trace port then you must use the nWAIT signal to stretch access
times.
All memory timing is defined by MCLK, and long access times can be accommodated
by stretching this clock. It is usual to stretch the LOW period of MCLK, as this allows
the memory manager to abort the operation if the access is eventually unsuccessful.
MCLK can be stretched before being applied to the processor, or the nWAIT input can
be used together with a free-running MCLK. Taking nWAIT LOW has the same effect
as stretching the LOW period of MCLK.
The pipelined nature of the processor bus interface means that there is a distinction
between clock cycles and bus cycles. nWAIT can be used to stretch a bus cycle, so that
it lasts for many clock cycles. The nWAIT input allows the timing of bus cycles to be
extended in increments of complete MCLK cycles:
•
•
nWAIT must only change during the LOW phase of MCLK.
In the pipeline, the address class signals and the memory request signals are ahead of
the data transfer by one bus cycle. In a system using nWAIT this can be more than one
MCLK cycle. This is illustrated in Figure 3-21 on page 3-30, which shows nWAIT
being used to extend a nonsequential cycle. In the example, the first N-cycle is followed
a few cycles later by another N-cycle to an unrelated address, and the address for the
second access is broadcast before the first access completes.
Modulating MCLK on page 3-29
Use of nWAIT to control bus cycles on page 3-29.
when nWAIT is HIGH on the falling edge of MCLK, a bus cycle completes
when nWAIT is LOW, the bus cycle is extended by stretching the low phase of
the internal clock.
Note
Copyright © 1994-2001. All rights reserved.
Memory Interface
3-29
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