RM9200 Atmel Corporation, RM9200 Datasheet - Page 56
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RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 56 of 284
- Download datasheet (2Mb)
Programmer’s Model
2.6.2
2-10
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
The Thumb-state register set
= banked register
CPSR
The Thumb-state register set is a subset of the ARM-state set. The programmer has
access to:
•
•
•
•
•
There are banked SPs, LRs, and SPSRs for each privileged mode. This register set is
shown in Figure 2-4.
SPSR_fiq
r0
r1
r2
r3
r4
r5
r6
r7
SP_fiq
LR_fiq
PC
Thumb-state general registers and program counter
CPSR
FIQ
8 general registers, r0–r7
the PC
the SP
the LR
the CPSR.
Thumb-state program status registers
Copyright © 1994-2001. All rights reserved.
Supervisor
SPSR_svc
r0
r1
r2
r3
r4
r5
r6
r7
SP_svc
LR_svc
PC
CPSR
Figure 2-4 Register organization in Thumb state
SPSR_abt
r0
r1
r2
r3
r4
r5
r6
r7
SP_abt
LR_abt
PC
CPSR
Abort
SPSR_irq
r0
r1
r2
r3
r4
r5
r6
r7
SP_irq
LR_irq
PC
CPSR
IRQ
ARM DDI 0029G
Undefined
SPSR_und
r0
r1
r2
r3
r4
r5
r6
r7
SP_und
LR_und
PC
CPSR
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