RM9200 Atmel Corporation, RM9200 Datasheet
RM9200
Specifications of RM9200
Related parts for RM9200
RM9200 Summary of contents
Page 1
ARM9TDMI Technical Reference Manual ARM DDI 0180A (Rev 3) ...
Page 2
ARM9TDMI Technical Reference Manual © Copyright ARM Limited 2000. All rights reserved. Release information Description March 2000 Proprietary notice ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited. The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ...
Page 3
Preface This preface introduces the ARM9TDMI (Revision 3), which is a member of the ARM family of general-purpose microprocessors. It contains the following sections: • About this document on page iv. • Further reading on page v. • Typographical conventions ...
Page 4
About this document This document is a reference manual for the ARM9TDMI microprocessor. The ARM9TDMI includes the following features: • The option, selectable using the UNIEN signal, of using two unidirectional buses DD[31:0] and DDIN[31:0], instead of a single bidirectional ...
Page 5
Further reading This section lists publications by ARM Limited, and by third parties. ARM publications ARM Architecture Reference Manual (ARM DDI 0100). ARM7TDMI Data Sheet (ARM DDI 0029). Other reading IEEE Std. 1149.1 - 1990, Standard Test Access Port and ...
Page 6
Typographical conventions The following typographical conventions are used in this document: bold italic typewriter typewriter typewriter italic typewriter bold vi Highlights ARM processor signal names within text, and interface elements such as menu names. May also be used for emphasis ...
Page 7
Feedback ARM Limited welcomes feedback both on the ARM9TDMI, and on the documentation. Feedback on this manual If you have any comments on this document, please send an email to giving: • the document title • the document number • ...
Page 8
Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 9
Contents ARM9TDMI Technical Reference Manual Preface About this document ......................................................................................................iv Further reading............................................................................................................... v Typographical conventions ............................................................................................vi Feedback ......................................................................................................................vii Chapter 1 Introduction 1.1 1.2 Chapter 2 Programmer’s Model 2.1 2.2 Chapter 3 ARM9TDMI Processor Core Memory Interface 3.1 3.2 3.3 3.4 ...
Page 10
Chapter 4 ARM9TDMI Coprocessor Interface 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Chapter 5 Debug Support 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 Chapter 6 Test Issues 6.1 6.2 Chapter ...
Page 11
Chapter 1 Introduction This chapter introduces the ARM9TDMI (Revision 3) and shows its processor block diagram under the headings: • About the ARM9TDMI on page 1-2. • Processor block diagram on page 1-3. ARM DDI 0180A © Copyright ARM Limited ...
Page 12
About the ARM9TDMI The ARM9TDMI is a member of the ARM family of general-purpose microprocessors. The ARM9TDMI is targeted at embedded control applications where high performance, low die size and low power are all important. The ARM9TDMI supports both ...
Page 13
Processor block diagram Figure 1-1 shows the ARM9TDMI processor block diagram. ID[..] Instruction Pipeline IDScan DIN[..] IINC REGBANK IAreg IAScan IA[..] Vectors RESULT[..] ARM DDI 0180A Instruction Decode and Datapath control logic Byte Rot DINFWD[..] / Sign Ex. Cmux ...
Page 14
Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 15
Chapter 2 Programmer’s Model This chapter describes the programmer’s model for the ARM9TDMI under the headings: • About the programmer’s model on page 2-2. • Pipeline implementation and interlocks on page 2-4. ARM DDI 0180A © Copyright ARM Limited 2000. ...
Page 16
About the programmer’s model The ARM9TDMI processor core implements ARM Architecture v4T, and so executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer’s model is fully described in the ARM Architecture Reference Manual. ...
Page 17
Instruction set extension spaces All ARM processors implement the undefined instruction space as one of the entry mechanisms for the Undefined Instruction Exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[ are UNDEFINED on all ...
Page 18
Pipeline implementation and interlocks 2.2 The ARM9TDMI implementation uses a five-stage pipeline design. These five stages are: • instruction fetch (F) • instruction decode (D) • execute (E) • data memory access (M) • register write (W). ARM implementations are ...
Page 19
Chapter 3 ARM9TDMI Processor Core Memory Interface This chapter describes the memory interface of the ARM9TDMI processor core. The processor core has a Harvard memory architecture, and so the memory interface is separated into the instruction interface and the data ...
Page 20
About the memory interface The ARM9TDMI has a Harvard bus architecture with separate instruction and data interfaces. This allows concurrent instruction and data accesses, and greatly reduces the CPI of the processor. For optimal performance, single cycle memory accesses ...
Page 21
It is not as critical for the instruction interface to have access to the data memory area unless the processor needs to execute code from data memory. 3.1.1 Actions of the ARM9TDMI in debug state Once the ARM9TDMI is in ...
Page 22
The system designer must take care when adding wait states because the interface is pipelined. When a wait state is asserted, the current data and instruction transfers are suspended. However, the address buses and control signals will have already changed ...
Page 23
Instruction interface Whenever an instruction enters the execute stage of the pipeline, a new opcode is fetched from the instruction bus. The ARM9TDMI processor core may be connected to a variety of cache/SRAM systems, and it is optimized for ...
Page 24
Internal cycles occur when the processor is stalled, either waiting for an interlock to resolve, or completing a multi-cycle instruction. A sequential cycle can occur immediately after an internal cycle. Figure 3-2 shows the cycle timing for an N followed ...
Page 25
Endian effects for instruction fetches The ARM9TDMI will perform 32-bit or 16-bit instruction fetches depending on whether the processor is in ARM or Thumb state. The processor state may be determined externally by the value of the ITBIT signal. ...
Page 26
Data interface Data transfers take place in the memory stage of the pipeline. The operation of the data interface is very similar to the instruction interface. The interface is pipelined with the address and control signals, becoming valid in ...
Page 27
The size of the transfer is indicated by DMAS[1:0]. These signals become valid at approximately the same time as the data address bus. The encoding is given below in Table 3-4: For coprocessor transfers, access to memory is not required, ...
Page 28
GCLK InMREQ ID[31:0] DnMREQ DSEQ DMORE DnRW DA[31:0] DD[31:0] DDIN[31:0] DABORT 3-10 LDM A A+4 A+8 © Copyright ARM Limited 2000. All rights reserved. MCR STR A+0xC A+0xC B Figure 3-3 Data access timings ARM DDI 0180A ...
Page 29
Unidirectional/bidirectional mode interface The ARM9TDMI supports connection to external memory systems using either a bidirectional data data bus or two unidirectional buses. This is controlled by the UNIEN input. If UNIEN is LOW, DD[31: tristate output bus ...
Page 30
Endian effects for data transfers The ARM9TDMI supports 32-bit, 16-bit and 8-bit data memory access sizes. The endian configuration of the processor, set by BIGEND, affects only non-word transfers (16-bit and 8-bit transfers). For data writes by the processor, ...
Page 31
ARM9TDMI reset behavior When nRESET is driven LOW, the currently executing instruction terminates abnormally. If GCLK is HIGH, InMREQ, ISEQ, DnMREQ, DSEQ and DMORE will asynchronously change to indicate an internal cycle. If GCLK is LOW, they will not ...
Page 32
GCLK nRESET InMREQ ISEQ IA[31:1] ID[31:0] DnMREQ DSEQ DMORE DnRW DA[31:0] 3-14 © Copyright ARM Limited 2000. All rights reserved 0x0 0x4 0x8 Figure 3-4 ARM9TDMI reset behavior ARM DDI 0180A M ...
Page 33
Chapter 4 ARM9TDMI Coprocessor Interface This chapter describes the ARM9TDMI coprocessor interface, and details the following operations: • About the coprocessor interface on page 4-2. • LDC/STC on page 4-3. • MCR/MRC on page 4-9. • Interlocked MCR on page ...
Page 34
About the coprocessor interface The ARM9TDMI supports the connection of coprocessors. All types of ARM coprocessor instructions are supported. Coprocessors determine the instructions they need to execute using a pipeline follower in the coprocessor. As each instruction arrives from ...
Page 35
LDC/STC The number of words transferred is determined by how the coprocessor drives the CHSD[1:0] and CHSE[1:0] buses. In the example, four words of data are transferred. Figure 4-1 on page 4-4 shows the ARM9TDMI LDC/STC cycle timing. ARM ...
Page 36
ARM Processor Pipeline Coprocessor Pipeline GCLK InMREQ ID[27:0] PASS LATECANCEL CHSD[1:0] CHSE[1:0] DD[31:0] STC DDIN[31:0] LDC DnMREQ DMORE DA[31:0] 4-4 Execute Execute Decode (GO) (GO) Execute Execute Decode (GO) LDC Figure 4-1 ARM9TDMI LDC / STC cycle ...
Page 37
As with all other instructions, the ARM9TDMI processor core performs the main decode off the rising edge of the clock during the decode stage. From this, the core commits to executing the instruction, and so performs an instruction fetch. The ...
Page 38
During the execute stage, the condition codes are combined with the flags to determine whether the instruction really executes or not. The output PASS is asserted (HIGH) if the instruction in the execute stage of the coprocessor pipeline: • is ...
Page 39
GO LAST For both MRC and STC instructions, the DDIN[31:0] bus is owned by the coprocessor, and can hence be driven by the coprocessor from the cycle after the relevant instruction enters the execute stage of the coprocessor pipeline, until ...
Page 40
Coprocessor handshake encoding Table 4-1 shows how the handshake signals CHSD[1:0] and CHSE[1:0] are encoded coprocessor is not attached to the ARM9TDMI, the handshake signals must be driven with “10” ABSENT, otherwise the ARM9TDMI processor will hang ...
Page 41
MCR/MRC These cycles look very similar to STC/LDC. An example, with a busy-wait state, is shown in Figure 4-3: ARM Processor Pipeline Coprocessor Pipeline GCLK ID[31:0] InMREQ PASS CHSD[1:0] CHSE[1:0] DD[31:0] MCR DDIN[31:0] MRC ARM DDI 0180A Execute Decode ...
Page 42
First InMREQ is driven LOW to denote that the instruction entering the decode stage of the pipeline. This causes the coprocessor to decode the new instruction and drive CHSD[1:0] as required. In the next cycle InMREQ is ...
Page 43
Interlocked MCR If the data for an MCR operation is not available inside the ARM9TDMI pipeline during its first decode cycle, the ARM9TDMI pipeline will interlock for one or more cycles until the data is available. An example of ...
Page 44
ARM Processor Pipeline Coprocessor Pipeline GCLK MCR/ ID[31:0] MRC InMREQ PASS LATECANCEL CHSD[1:0] CHSE[1:0] DD[31:0] MCR DDIN[31:0] MRC 4-12 Decode Execute Decode (interlock) (WAIT) Execute Decode Decode (WAIT) WAIT WAIT LAST © Copyright ARM Limited 2000. All rights reserved. Execute ...
Page 45
CDP CDP signals normally execute in a single cycle. Like all the previous cycles, InMREQ is driven LOW to signal when an instruction is entering the decode and then the execute stage of the pipeline: • if the instruction ...
Page 46
LDR with Data Abort CDP: ARM Processor Pipeline CDP: Coprocessor Pipeline GCLK ID[31:0] CPRT InMREQ PASS LATECANCEL CHSD[1:0] CHSE[1:0] DABORT 4-14 Execute Memory Decode Execute Decode Execute LAST Ignored © Copyright ARM Limited 2000. All rights reserved. Exception Exception Entry ...
Page 47
Privileged instructions The coprocessor may restrict certain instructions for use in privileged modes only this, the coprocessor will have to track the InTRANS output. InTRANS changes after a mode change. Mode Change CDP: ARM Processor Pipeline CDP: ...
Page 48
Busy-waiting and interrupts The coprocessor is permitted to stall, or busy-wait, the processor during the execution of a coprocessor instruction if, for example still busy with an earlier coprocessor instruction so, the coprocessor associated with ...
Page 49
Coprocessor 15 MCRs Coprocessor 15 is typically reserved for use as a system control coprocessor. For an MCR to coprocessor 15 possible to transfer the coprocessor data to the coprocessor on the IA and DA buses. To ...
Page 50
Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 51
Chapter 5 Debug Support This chapter describes the debug support for the ARM9TDMI, including the EmbeddedICE macrocell: • About debug on page 5-2. • Debug systems on page 5-3. • Debug interface signals on page 5-5. • Scan chains and ...
Page 52
About debug The ARM9TDMI debug interface is based on IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture. Please refer to this standard for an explanation of the terms used in this chapter and for a description ...
Page 53
Debug systems The ARM9TDMI forms one component of a debug system that interfaces from the high-level debugging performed by the user to the low-level interface supported by the ARM9TDMI. A typical system is shown in Figure 5-1: Such a ...
Page 54
The ARM9TDMI The ARM9TDMI, with hardware extensions to ease debugging, is the lowest level of the system. The debug extensions allow the user to stall the core from program execution, examine its internal state and the state of the ...
Page 55
Debug interface signals There are four primary external signals associated with the debug interface: • IEBKPT, DEWPT, and EDBGRQ, with which the system asks the ARM9TDMI to enter debug state • DBGACK, which the ARM9TDMI uses to flag back ...
Page 56
GCLK IA[31:0] ID[31:0] 1 IEBKPT DBGACK 5.3.2 Breakpoints and exceptions A breakpointed instruction may have a prefetch abort associated with it. If so, the prefetch abort takes priority and the breakpoint is ignored. (If there is a ...
Page 57
This means that the instruction which was previously breakpointed is fetched again, and if the breakpoint is still set, the processor enters debug state once it reaches the execute stage of the pipeline. Once the processor has entered debug state, ...
Page 58
CLK nMREQ D[31: A[31:0] D[31:0] DIN[31:0] atchpoint BGACK 5 FDp DDp EDp Fldr Dldr Eldr Mldr wldr LDR Figure 5-3 Watchpoint ...
Page 59
FB Fldr Dldr GCLK InMREQ IA[31:1] A A+4 ID[31:0] LDR B DA[31:0] DD[31:0] DDIN[31:0] Watchpoint DBGACK ARM DDI 0180A Eldr Mldr Wldr A T+1 © Copyright ARM Limited 2000. ...
Page 60
Watchpoints and exceptions If there is an abort with the data access as well as a watchpoint, the watchpoint condition is latched, the exception entry sequence performed, and then the processor enters debug state. If there is an interrupt ...
Page 61
Scan chains and JTAG interface There are three scan chains inside the ARM9TDMI. These allow testing, debugging and programming of the EmbeddedICE macrocell watchpoint units. The scan chains are controlled by a JTAG-style Test Access Port (TAP) controller. In ...
Page 62
The JTAG state machine The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure 5-5 shows the state transitions that occur in the TAP controller. The state numbers are also shown ...
Page 63
Reset The JTAG interface includes a state-machine controller (the TAP controller). In order to force the TAP controller into the correct state after power-up of the device, a reset pulse must be applied to the nTRST signal. If the ...
Page 64
Public instructions The following public instructions are supported: In the descriptions that follow, TDI and TMS are sampled on the rising edge of TCK and all output transitions on TDO occur as a result of the falling edge of ...
Page 65
SCAN_N (0010) This instruction connects the scan path select register between TDI and TDO. During the CAPTURE-DR state, the fixed value 10000 is loaded into the register. During the SHIFT-DR state, the ID number of the desired scan path is ...
Page 66
BYPASS (1111) The BYPASS instruction connects a 1-bit shift register (the bypass register) between TDI and TDO. When the BYPASS instruction is loaded into the instruction register, all the scan cells are placed in their normal (system) mode of operation. ...
Page 67
When the HIGHZ instruction is loaded into the instruction register, all ARM9TDMI outputs are driven to the high impedance state and the external HIGHZ signal is driven HIGH. This the signal TBE had been driven LOW. In ...
Page 68
RESTART (0100) This instruction is used to restart the processor on exit from debug state. The RESTART instruction connects the bypass register between TDI and TDO and the TAP controller behaves as if the BYPASS instruction had been loaded. The ...
Page 69
Test data registers The following test data registers may be connected between TDI and TDO: • Bypass register. • ARM9TDMI device identification (ID) code register. • Instruction register on page 5-20. • Scan chain select register on page 5-20. ...
Page 70
The IEEE format of the ID register is as shown in Figure 5-2: 5.6.3 Instruction register Purpose Length Operating mode During the CAPTURE-IR state, the value 0b0001 is loaded into this register. This is shifted out during SHIFT-IR (least significant ...
Page 71
The currently selected scan chain only changes when a SCAN_N instruction is executed reset occurs. On reset, scan chain 3 is selected as the active scan chain. The number of the currently selected scan chain is reflected on ...
Page 72
Scan chains and 3 These allow serial access to the core logic, and to the EmbeddedICE macrocell for programming purposes. Each scan cell is fairly simple and can perform two basic functions, capture and shift. Scan ...
Page 73
Scan chain 1 Purpose Length This scan chain is 67 bits long, 32 bits for data values, 32 bits for instruction data, and three additional bits, SYSSPEED, DDEN and an used bit. The three bits serve four different purposes: • ...
Page 74
Scan chain 2 Purpose Length To access this serial register, scan chain 2 must first be selected via the SCAN_N TAP controller instruction. The TAP controller must then be placed in INTEST mode. No action is taken during CAPTURE-DR. During ...
Page 75
Scan chain 3 Purpose Length Scan chain 3 is provided so that an optional external boundary scan chain may be controlled via the ARM9TDMI. Typically this would be used for a scan chain around the pad ring of a packaged ...
Page 76
ARM9TDMI core clocks The ARM9TDMI has two clocks, the memory clock GCLK, and an internally TCK generated clock, DCLK. During normal operation, the core is clocked by GCLK, and internal logic holds DCLK LOW. When the ARM9TDMI is in ...
Page 77
Clock switching during debug When the ARM9TDMI enters debug state, it must switch from GCLK to DCLK. This is handled automatically by logic in the ARM9TDMI. On entry to debug state, the ARM9TDMI asserts DBGACK in the HIGH phase ...
Page 78
Clock switching during test When under serial test conditions, when test patterns are being applied to the core through the JTAG interface, the ARM9TDMI must be clocked using DCLK. Entry into test is less automatic than debug and some ...
Page 79
Determining the core state and system state When the ARM9TDMI is in debug state, the core state and system state may be examined. This is done by forcing load and store multiples into the pipeline. Before the core state ...
Page 80
After determining the values in the current bank of registers, it may be desirable to access banked registers. This can only be done by changing mode. Normally, a mode change may only occur if the core is already in a ...
Page 81
After the system speed instructions have been scanned into the instruction data bus and clocked into the pipeline, the RESTART instruction must be loaded into the TAP controller. This will cause the ARM9TDMI automatically to resynchronize back to GCLK when ...
Page 82
Exit from debug state Leaving debug state involves restoring the internal state of the ARM9TDMI, causing a branch to the next instruction to be executed, and synchronizing back to GCLK. After restoring the internal state, a branch instruction must ...
Page 83
DBGACK may remain HIGH for more than three instruction fetches, if precise instruction access counting is required, some external logic must generate a modified DBGACK that always falls after three instruction fetches. When a system speed access occurs, DBGACK remains ...
Page 84
GCLK InMREQ ISEQ IA[31:0] ID[31:0] IEBKPT DBGACK 5-34 Memory Cycles 1 © Copyright ARM Limited 2000. All rights reserved. Internal Cycles 2 3 Figure 5-8 Debug state entry ARM DDI 0180A ...
Page 85
The behavior of the program counter during debug To force the ARM9TDMI to branch back to the place at which program flow was interrupted by debug, the debugger must keep track of what happens to the PC. There are ...
Page 86
Watchpoint with another exception If a watchpoint access simultaneously causes a data abort, the ARM9TDMI will enter debug state in abort mode. Entry into debug is held off until the core has changed into abort mode, and fetched the ...
Page 87
System speed accesses If a system speed access is performed during debug state, the value of the PC is increased by five addresses. Since system speed instructions access the memory system possible for aborts to take place. ...
Page 88
EmbeddedICE macrocell The EmbeddedICE macrocell is integral to the ARM9TDMI processor core. It has two hardware breakpoint/watchpoint units each of which may be configured to monitor either the instruction memory interface or the data memory interface. Each watchpoint unit ...
Page 89
Address 01000 01001 01010 01011 01100 01101 10000 10001 10010 10011 10100 10101 ARM DDI 0180A Table 5-4 ARM9TDMI EmbeddedICE macrocell register map (continued) Width Function 32 Watchpoint 0 address value 32 Watchpoint 0 address mask 32 Watchpoint 0 data ...
Page 90
Scan Chain Register R Address Address Decoder Data 0 TDI TDO For example watchpoint is requested on a particular memory location but the data value is irrelevant, the data mask register can be ...
Page 91
Control registers The format of the control registers depends on how bit 3 is programmed. If bit 3 is programmed the breakpoint comparators examine the data address, data and control signals. In this case, the format ...
Page 92
Table 5-5 Watchpoint control register for data comparison bit functions (continued) Bit CHAIN RANGE ENABLE If bit 3 of the control register is programmed to 0, the comparators will examine the instruction address, instruction data and instruction control buses. In ...
Page 93
Table 5-6 Watchpoint control register for instruction comparison bit functions Bit ITBIT InTRANS EXTERN CHAIN RANGE ENABLE ARM DDI 0180A Function Compares against the Thumb state signal from the core to determine between a Thumb (ITBIT = 1) instruction fetch ...
Page 94
Debug control register The ARM9TDMI debug control register is four bits wide and is shown in Figure 5-12: 3 Single step Bit 3 controls the single-step hardware, and this is explained in more detail in Single stepping on page ...
Page 95
Vector catch register The ARM9TDMI EmbeddedICE macrocell controls logic to enable accesses to the exception vectors to be trapped in an efficient manner. This is controlled by the vector catch register, as shown in Figure 5-14. The functionality is ...
Page 96
Vector catching The ARM9TDMI EmbeddedICE macrocell contains logic that allows efficient trapping of fetches from the vectors during exceptions. This is controlled by the Vector catch register. If one of the bits in this register is set HIGH and ...
Page 97
Single stepping The ARM9TDMI EmbeddedICE macrocell contains logic that allows efficient single stepping through code. This leaves the macrocell watchpoint comparators free for general use. This function is enabled by setting bit 3 of the debug control register. The ...
Page 98
Debug communications channel The ARM9TDMI EmbeddedICE macrocell contains a communication channel for passing information between the target and the host debugger. This is implemented as coprocessor 14. The communications channel consists of a 32-bit wide comms data read register, ...
Page 99
Bit 0 From the debugger’s point of view, the registers are accessed via the scan chain in the usual way. From the processor, these registers are accessed via coprocessor register transfer instructions. The following instructions should be used: MRC p14, ...
Page 100
When the W bit is clear, a message is written by a register transfer to coprocessor 14. As the data transfer occurs from the processor to the comms data write register, the W bit is set in the debug comms ...
Page 101
Chapter 6 Test Issues This chapter examines the test issues for the ARM9TDMI and lists the scan chain 0 bit order under the headings: • About testing on page 6-2. • Scan chain 0 bit order on page 6-3. ARM ...
Page 102
About testing The ARM9TDMI processor core supports parallel and serial test methodologies. The parallel test patterns are derived from assembler ARM code programs written to achieve a high fault coverage. The ARM9TDMI processor core has a fully JTAG-compatible scan ...
Page 103
Scan chain 0 bit order ARM DDI 0180A © Copyright ARM Limited 2000. All rights reserved. Table 6-1 Scan chain 0 bit order Number Signal Direction 1 ID[0] Input 2 ID[1] Input 3:31 ID[2:30] Input 32 ID[31] Input 33 ...
Page 104
Table 6-1 Scan chain 0 bit order (continued) © Copyright ARM Limited 2000. All rights reserved. Number Signal Direction 136 COMMRX Output 137 COMMTX Output 138 DBGACK Output 139 RANGEOUT0 Output 140 RANGEOUT1 Output 141 DBGRQI Output 142 DDBE ...
Page 105
ARM DDI 0180A Table 6-1 Scan chain 0 bit order (continued) © Copyright ARM Limited 2000. All rights reserved. Number Signal Direction 161 ISYNC Input 162 BIGEND Input 163 HIVECS Input 164 CHSD[1] Input 165 CHSD[0] Input 166 CHSE[1] Input ...
Page 106
Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 107
Chapter 7 Instruction Cycle Summary and Interlocks This chapter gives the instruction cycle times and shows the timing diagrams for interlock timing: • Instruction cycle times on page 7-2. • Interlocks on page 7-5. ARM DDI 0180A © Copyright ARM ...
Page 108
Instruction cycle times Key to tables Symbol Table 7-2 summarizes the ARM9TDMI instruction cycle counts and bus activity when executing the ARM instruction set. Instruction Cycles Data Op 1 Data Op 2 ...
Page 109
Instruction Cycles LDR 5 STR 1 LDM 2 LDM n LDM n+4 STM 2 STM n SWP 2 SWP SWI, Undefined 3 CDP b+1 LDC, STC b+n MCR b+1 MRC b+1 MRC b+2 MRC b+3 ...
Page 110
Table 7-3 shows the instruction cycle times from the perspective of the data bus: 7.1.1 Multiplier cycle counts The number of cycles that a multiply instruction takes to complete depends on which instruction it is, and on the value of ...
Page 111
Interlocks Pipeline interlocks occur when the data required for an instruction is not available due to the incomplete execution of an earlier instruction. When an interlock occurs, instruction fetches stop on the instruction memory interface of the ARM9TDMI. Four ...
Page 112
Example 2 In this second example, the following code sequence is executed: LDRB R0, [R1,#1] ADD R2, R0, R1 Now, because a rotation must occur on the loaded data, there is a second interlock cycle. The behavior on the instruction ...
Page 113
Example 3 In this third example, the following code sequence is executed: LDM R12,{R1-R3} ADD R2, R2, R1 The LDM takes three cycles to execute in the memory stage of the pipeline. The ADD is therefore delayed until the LDM ...
Page 114
Example 4 In the fourth example, the following code sequence is executed: LDM R12,{R1-R3} ADD R4, R3, R1 The code is the same code as in example 3, but in this instance the ADD instruction uses R3. Due to the ...
Page 115
Chapter 8 ARM9TDMI AC Characteristics This chapter gives the timing diagrams and timing parameters for the ARM9TDMI: • ARM9TDMI timing diagrams on page 8-2. • ARM9TDMI timing parameters on page 8-14. ARM DDI 0180A © Copyright ARM Limited 2000. All ...
Page 116
ARM9TDMI timing diagrams CLK A[31:1] T IAH nMREQ T IMQH nM[4:0] T INMH nTRANS T ITRSH SEQ T ISQH TBIT T ITBH ABE A[31:1] nM[4:0] nTRANS 8-2 T IAD T IMQD T INMD T ITRSD T ISQD T ITBD ...
Page 117
GCLK ID[31:0] IABORT IEBKPT ARM DDI 0180A T IDS T IABS Figure 8-3 ARM9TDMI instruction memory interface input timing © Copyright ARM Limited 2000. All rights reserved. T IDH T IABH T IBKS T IBKH 8-3 ...
Page 118
CLK A[31:0] T DAH LOCK T DLKH nM[4:0] T DNMH nTRANS T DTRSH SEQ T DSQH MORE T DMRH MAS[1:0] T DMSH nRW T DRWH 8-4 T DAD T DLKD T DNMD T DTRSD T DSQD T DMRD T DMSD ...
Page 119
DABE DA[31:0],DnRW DnM[4:0],DnTRANS DMAS[1:0],DLOCK GCLK DABORT DnMREQ T DMQH GCLK DDIN[31:0] DD[31:0] DEWPT ARM DDI 0180A T DABZ Figure 8-5 ARM9TDMI data address bus timing T T DABTD Figure 8-6 ARM9TDMI data ABORT and DnMREQ timing T DDS T DDOH ...
Page 120
DBE D[31:0] CLK FIQ IRQ SYNC IGEND IVECS NIEN WAIT RESET 8-6 T DDBZ T INTS T ISYS T BIGS T HIVS T UNIS T NWS T RSTS Figure 8-9 ARM9TDMI miscellaneous signal timing © Copyright ARM Limited 2000. All ...
Page 121
GCLK PASS T PASH LATECANCEL CHSD[1:0] CHSE[1:0] ARM DDI 0180A T PASD T LTCH T CHSS Figure 8-10 ARM9TDMI coprocessor interface signal timing © Copyright ARM Limited 2000. All rights reserved. T LTCD T CHSH 8-7 ...
Page 122
TCK TCK1 T TCKR TCK2 T TCKF IR[3:0] SCREG[3:0] TAPSM[3:0] T TPMH TDO nTDOEN 8-8 T IRSH T TPMD T TDOH T TOEH Figure 8-11 ARM9TDMI JTAG output signals © Copyright ARM Limited 2000. All rights reserved. T TCKF T ...
Page 123
TCK ECAPCLKBS ICAPCLKBS PCLKBS RSTCLKBS SHCLK1BS T SHKR SHCLK2BS T SHKF DRIVEOUTBS SDIN T SDNH SDOUTBS TDO ARM DDI 0180A T CAPR T BRTD T T DRBSH T SDND Figure 8-12 ARM9TDMI external boundary scan chain output signals T TDSH ...
Page 124
TRST STCLKBS 8-10 T BRST Figure 8-14 ARM9TDMI nTRST to RSTCLKBS relationship T TDIS Figure 8-15 ARM9TDMI JTAG input signal timing © Copyright ARM Limited 2000. All rights reserved. T TDIH ARM DDI 0180A ...
Page 125
GCLK ECLK T GEKR COMMTX COMMRX T COMH DBGACK T DCKH RANGEOUT0 RANGEOUT1 INSTREXEC EXTERN0 EXTERN1 EDBGRQ ARM DDI 0180A T T COMD T DCKD T RG0H T RG1H T INXH T EXTS T DBQS Figure 8-16 ARM9TDMI GCLK related ...
Page 126
CK CLK T TEKF BGRQI T DGIH TRST BGRQI DBGRQ BGRQI 8-12 T DGID Figure 8-17 ARM9TDMI TCK related debug output timings T DQIR Figure 8-18 ARM9TDMI nTRST to DBGRQI relationship T EDQH Figure 8-19 ARM9TDMI EDBGRQ to DBGRQI relationship ...
Page 127
DBGEN RANGEOUT0 RANGEOUT1 DBGRQI ARM DDI 0180A T RGEN T DQEN Figure 8-20 ARM9TDMI DBGEN to output effects © Copyright ARM Limited 2000. All rights reserved. 8-13 ...
Page 128
ARM9TDMI timing parameters Timing parameter Description Tbigh BIGEND hold time from GCLK falling Tbigs BIGEND setup time to GCLK falling Tbrst Delay from nTRST falling to RSTCLKBS rising Tbrtd RSTCLKBS rising from TCK falling Tbrth RSTCLKBS falling from TCK ...
Page 129
Timing parameter Description Tdckd DBGACK output delay Tdckh DBGACK output hold time Tddbe Delay from DDBE rising to DD[31:0] (output) driven valid Tddbz Delay from DDBE falling to DD[31:0] (output) high impedance Tddend DDEN delay from GCLK falling Tddenh DDEN ...
Page 130
Timing parameter Description Tdqir nTRST falling to DBGRQI falling delay Tdrbsd DRIVEOUTBS delay from TCK falling Tdrbsh DRIVEOUTBS hold time from TCK falling Tdrwd DnRW delay from GCLK rising Tdrwh DnRW hold time from GCLK rising Tdsqd DSEQ delay from ...
Page 131
Timing parameter Description Tiad IA[31:1] delay from GCLK rising Tiah IA[31:1] hold time from GCLK rising Tibkh IEBKPT hold time from GCLK rising Tibks IEBKPT setup time to GCLK rising Tidh ID[31:0] hold time from GCLK falling Tids ID[31:0] setup ...
Page 132
Timing parameter Description Tltch LATECANCEL hold time from GCLK falling Tnwh nWAIT hold time from GCLK rising Tnws nWAIT setup time to GCLK falling Tpasd PASS output delay from GCLK rising Tpash PASS hold time from GCLK rising Trg0d RANGEOUT0 ...
Page 133
Timing parameter Description Ttdoh TDO hold time from TCK falling Ttdsd TDO delay from SDOUTBS changing Ttdsh TDO hold time from SDOUTBS changing Ttekf TCK falling to ECLK falling delay Ttekr TCK rising to ECLK rising delay Ttoed nTDOEN output ...
Page 134
Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 135
Appendix A ARM9TDMI Signal Descriptions This chapter lists and describes the ARM9TDMI signals: • Instruction memory interface signals on page A-2. • Data memory interface signals on page A-3. • Coprocessor interface signals on page A-5. • JTAG and TAP ...
Page 136
Instruction memory interface signals A.1 Name Direction Description IA[31:1] Output Instruction Address Bus. This is the processor instruction address bus. It changes when GCLK is HIGH. IABE Input Instruction Address Bus Enable. This is an input which, when LOW, it ...
Page 137
Data memory interface signals A.2 Name Direction DA[31:0] Output DABE Input DABORT Input DD[31:0] Output DDBE Input DDEN Output DDIN[31:0] Input DLOCK Output DMAS[1:0] Output DMORE Output DnM[4:0] Output DnMREQ Output ARM DDI 0180A Description Data Address Bus. This is ...
Page 138
Name Direction DnRW Output DnTRANS Output DSEQ Output A-4 Table A-2 Data memory interface signals (continued) Description Data not Read, Write. If LOW at the end of phase 2, any data memory access in the following cycle is a read. ...
Page 139
Coprocessor interface signals A.3 Name Direction CHSD[1:0] Input CHSE[1:0] Input LATECANCEL Output PASS Output For further information on the coprocessor interface refer to Chapter 4 ARM9TDMI Coprocessor Interface. ARM DDI 0180A Description Coprocessor Handshake Decode. The handshake signals from the ...
Page 140
JTAG and TAP controller signals A.4 Name Direction DRIVEOUTBS Output ECAPCLKBS Output ICAPCLKBS Output IR[3:0] Output PCLKBS Output RSTCLKBS Output SCREG[4:0] Output SDIN Output SDOUTBS Input A-6 Description Boundary Scan Cell Enable. This signal is used to control the multiplexers ...
Page 141
Name Direction SHCLK1BS Output SHCLK2BS Output TAPID[31:0] Input TAPSM[3:0] Output TCK Input TCK1 Output TCK2 Output TDI Input TDO Output nTDOEN Output TMS Input nTRST Input ARM DDI 0180A Table A-4 JTAG and TAP controller signals (continued) Description Boundary Scan ...
Page 142
Debug signals A.5 Name Direction Description COMMRX Output Communications Channel Receive. When HIGH, this signal denotes that the comms channel receive buffer contains data waiting to be read by the ARM9TDMI. COMMTX Output Communications Channel Transmit. When HIGH, this signal ...
Page 143
Name Direction Description RANGEOUT0 Output EmbeddedICE Rangeout 0. This signal indicates that the EmbeddedICE macrocell watchpoint unit 0 has matched the conditions currently present on the address, data and control buses. This signal is independent of the state of the ...
Page 144
Miscellaneous signals A.6 Name Direction Description BIGEND Input Big-Endian Configuration. When this input is HIGH, the ARM9TDMI processor treats bytes in memory as being in big- endian format. When it is LOW, memory is treated as little-endian. ECLK Output External ...
Page 145
Name Direction Description nWAIT Input Not Wait. When a memory request cannot be processed in a single cycle, the ARM9TDMI can be made to wait for a number of GCLK cycles by driving nWAIT LOW. Internally, the inverse of nWAIT ...
Page 146
A-12 © Copyright ARM Limited 2000. All rights reserved. ARM DDI 0180A ...
Page 147
Index The items in this index are listed in alphabetic order, with symbols and numerics appearing at the end. The references given are to page numbers. A About testing 6-2 ARM instruction set 1-2 ARM7TDMI code compatibility 2-2 B bidirectional ...
Page 148
Index data transfer 3-8 16-bit 3-12 32-bit 3-12 8-bit 3-12 aborted 3-8 access timings 3-9 coprocessor transfers 3-9 cycle encoding 3-8 data abort vector 3-8 data cycle 3-8 direction 3-8 endian configuration 3-12 endian effects 3-12 memory access sizes 3-12 ...
Page 149
R reset memory interface 3-13 S scan chains 5-11, 5-22 external 5-21 scan chain 0 5-22 scan chain 0 bit order 6-1, 6-3 scan chain 1 5-23 scan chain 2 5-24 scan chain 3 5-25 serial test and debug 5-12 ...