RM9200 Atmel Corporation, RM9200 Datasheet - Page 38

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4-6
During the execute stage, the condition codes are combined with the flags to determine
whether the instruction really executes or not. The output PASS is asserted (HIGH) if
the instruction in the execute stage of the coprocessor pipeline:
•
•
If a coprocessor instruction busy-waits, PASS is asserted on every cycle until the
coprocessor instruction is executed. If an interrupt occurs during busy-waiting, PASS
is driven LOW, and the coprocessor will stop execution of the coprocessor instruction.
A further output, LATECANCEL, is used to cancel a coprocessor instruction when the
instruction preceding it caused a data abort. This is valid on the rising edge of GCLK
on the cycle that follows the first execute cycle of the coprocessor instructions. This is
the only cycle in which LATECANCEL can be asserted.
On the falling edge of the clock, the ARM9TDMI processor core examines the
coprocessor handshake signals CHSD[1:0] or CHSE[1:0]:
•
•
The handshake signals encode one of four states:
ABSENT
WAIT
is a coprocessor instruction
has passed its condition codes.
If a new instruction is entering the execute stage in the next cycle, it examines
CHSD[1:0].
If the currently executing coprocessor instruction requires another execute cycle,
it examines CHSE[1:0].
© Copyright ARM Limited 2000. All rights reserved.
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM9TDMI processor core takes the undefined instruction
trap.
If there is a coprocessor attached that can handle the instruction, but not
immediately, the coprocessor handshake signals are driven to indicate
that the ARM9TDMI processor core should stall until the coprocessor
can catch up. This is known as the busy-wait condition. In this case, the
ARM9TDMI processor core loops in an idle state waiting for CHSE[1:0]
to be driven to another state, or for an interrupt to occur.
If CHSE[1:0] changes to ABSENT, the undefined instruction trap will
be taken.
If CHSE[1:0] changes to GO or LAST, the instruction will proceed as
described below.
If an interrupt occurs, the ARM9TDMI processor core is forced out of the
busy-wait state. This is indicated to the coprocessor by the PASS signal
going LOW. The instruction will be restarted at a later date and so the
ARM DDI 0180A