RM9200 Atmel Corporation, RM9200 Datasheet - Page 99

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.16.2
ARM DDI 0180A
Communications via the comms channel
The Thumb instruction set does not support coprocessors so the ARM9TDMI must be
operated in ARM state in order to access the debug comms channel.
Bit 0
From the debugger’s point of view, the registers are accessed via the scan chain in the
usual way. From the processor, these registers are accessed via coprocessor register
transfer instructions. The following instructions should be used:
MRC p14, 0, Rd, c0, c0, 0
Returns the debug comms control register into Rd.
MCR p14, 0, Rn, c1, c0, 0
Writes the value in Rn to the comms data write register.
MRC p14, 0, Rd, c1, c0, 0
Returns the debug data read register into Rd.
There are two methods of communicating via the comms channel, transmitting and
receiving. The following descriptions detail their usage.
Sending a message to the debugger
When the processor wishes to send a message to the debugger, it must check the comms
data write register is free for use by finding out whether the W bit of the debug comms
control register is clear.
It reads the debug comms control register to check status of the W bit.
•
•
If the W bit is set, previously written data has not been read by the debugger. The
processor must continue to poll the control register until the W bit is clear.
If W bit is clear, the comms data write register is clear.
Note
© Copyright ARM Limited 2000. All rights reserved.
Denotes whether there is some new data in the comms data read register.
If, from the processor’s point of view, R=1, there is some new data which
may be read via an MRC instruction.
If, from the debugger’s point of view, R=0, the comms data read register
is free and new data may be placed there through the scan chain.
If R=1, this denotes that data previously placed there through the scan
chain has not been collected by the processor, and so the debugger must
wait.
5-49