RM9200 Atmel Corporation, RM9200 Datasheet - Page 91

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.13.3
ARM DDI 0180A
8
ENABLE
Control registers
7
RANGE
Bit 8 and bit 3 cannot be masked.
The format of the control registers depends on how bit 3 is programmed. If bit 3 is
programmed to be 1, the breakpoint comparators examine the data address, data and
control signals.
In this case, the format of the register is as shown in Figure 5-10.
The bits have the following functions:
6
CHAIN
Bit
DnRW
DMAS[1:0]
DnTRANS
EXTERN
Note
© Copyright ARM Limited 2000. All rights reserved.
Table 5-5 Watchpoint control register for data comparison bit functions
5
EXTERN
Function
Compares against the data not read/write signal from the core in order to
detect the direction of the data data bus activity. nRW is 0 for a read, and 1
for a write.
Compares against the DMAS[1:0] signal from the core in order to detect the
size of the data data bus activity.
Compares against the data not translate signal from the core in order to
determine between a user mode (DnTRANS = 0) data transfer, and a
privileged mode (DnTRANS = 1) transfer.
Is an external input into the EmbeddedICE macrocell that allows the
watchpoint to be dependent upon some external condition. The EXTERN
input for watchpoint 0 is labelled EXTERN0, and the EXTERN input for
watchpoint 1 is labelled EXTERN1.
Figure 5-10 Watchpoint control register for data comparison
4
DnTRANS
3
1
2
DMAS[1]
1
DMAS[0]
0
DnRW
5-41