RM9200 Atmel Corporation, RM9200 Datasheet - Page 67

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Support
When the HIGHZ instruction is loaded into the instruction register, all ARM9TDMI
outputs are driven to the high impedance state and the external HIGHZ signal is driven
HIGH. This is as if the signal TBE had been driven LOW.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the
SHIFT-DR state, test data is shifted into the bypass register via TDI and out via TDO
after a delay of one TCK cycle. The first bit shifted out will be a zero.
The bypass register is not affected in the UPDATE-DR state.
CLAMPZ (1001)
This instruction connects a 1-bit shift register (the bypass register) between TDI and
TDO.
When the CLAMPZ instruction is loaded into the instruction register and scan chain 0
is selected, all the 3-state outputs (as described above) are placed in their inactive state,
but the data supplied to the outputs is derived from the scan cells. The purpose of this
instruction is to ensure that, during production test, each output can be disabled when
its data value is either a logic 0 or logic 1.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register via TDI and out via
TDO after a delay of one TCK cycle. The first bit shifted out will be a zero.
The bypass register is not affected in the UPDATE-DR state.
SAMPLE/PRELOAD (0011)
When the instruction register is loaded with the SAMPLE/PRELOAD instruction, all
the scan cells of the selected scan chain are placed in the normal mode of operation.
In the CAPTURE-DR state, a snapshot of the signals of the boundary scan is taken on
the rising edge of TCK. Normal system operation is unaffected.
In the SHIFT-DR state, the sampled test data is shifted out of the boundary scan via the
TDO pin, while new data is shifted in via the TDI pin to preload the boundary scan
parallel input latch. Note that this data is not applied to the system logic or system pins
while the SAMPLE/PRELOAD instruction is active.
This instruction should be used to preload the boundary scan register with known data
prior to selecting INTEST or EXTEST instructions.
ARM DDI 0180A
© Copyright ARM Limited 2000. All rights reserved.
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