RM9200 Atmel Corporation, RM9200 Datasheet - Page 110
RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
7.1.1
7-4
Multiplier cycle counts
Table 7-3 shows the instruction cycle times from the perspective of the data bus:
The number of cycles that a multiply instruction takes to complete depends on which
instruction it is, and on the value of the multiplier-operand. The multiplier-operand is
the contents of the register specified by bits [8:11] of the ARM multiply instructions, or
bits [2:0] of the Thumb multiply instructions.
•
•
For ARM MUL, MLA, SMULL, SMLAL, and Thumb MUL, m is:
1 if bits [31:8] of the multiplier operand are all zero or one
2 if bits [31:16] of the multiplier operand are all zero or one
3 if bits [31:24] of the multiplier operand are all zero or all one
4 otherwise.
For ARM UMULL, UMLAL, m is:
1 if bits [31:8] of the multiplier operand are all zero
2 if bits [31:16] of the multiplier operand are all zero
3 if bits [31:24] of the multiplier operand are all zero
4 otherwise.
© Copyright ARM Limited 2000. All rights reserved.
Instruction
LDR
STR
LDM,STM
SWP
LDC, STC
MCR,MRC
Table 7-3 Data bus instruction times
Cycle time
1N
1N
1N+(n-1)S
1N+1S
1N+(n-1)S
1C
ARM DDI 0180A