RM9200 Atmel Corporation, RM9200 Datasheet - Page 10

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

x
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Appendix A
ARM9TDMI Coprocessor Interface
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Debug Support
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
Test Issues
6.1
6.2
Instruction Cycle Summary and Interlocks
7.1
7.2
ARM9TDMI AC Characteristics
8.1
8.2
ARM9TDMI Signal Descriptions
A.1
A.2
A.3
A.4
A.5
A.6
© Copyright ARM Limited 2000. All rights reserved.
About the coprocessor interface................................................................... 4-2
LDC/STC ...................................................................................................... 4-3
MCR/MRC .................................................................................................... 4-9
Interlocked MCR......................................................................................... 4-11
CDP ............................................................................................................ 4-13
Privileged instructions................................................................................. 4-15
Busy-waiting and interrupts ........................................................................ 4-16
Coprocessor 15 MCRs ............................................................................... 4-17
About debug ................................................................................................. 5-2
Debug systems............................................................................................. 5-3
Debug interface signals ................................................................................ 5-5
Scan chains and JTAG interface ................................................................ 5-11
The JTAG state machine............................................................................ 5-12
Test data registers...................................................................................... 5-19
ARM9TDMI core clocks.............................................................................. 5-26
Clock switching during debug..................................................................... 5-27
Clock switching during test ......................................................................... 5-28
Determining the core state and system state ............................................. 5-29
Exit from debug state.................................................................................. 5-32
The behavior of the program counter during debug ................................... 5-35
EmbeddedICE macrocell............................................................................ 5-38
Vector catching........................................................................................... 5-46
Single stepping ........................................................................................... 5-47
Debug communications channel ................................................................ 5-48
About testing................................................................................................. 6-2
Scan chain 0 bit order................................................................................... 6-3
Instruction cycle times .................................................................................. 7-2
Interlocks ...................................................................................................... 7-5
ARM9TDMI timing diagrams ........................................................................ 8-2
ARM9TDMI timing parameters ................................................................... 8-14
Instruction memory interface signals ............................................................ A-2
Data memory interface signals ..................................................................... A-3
Coprocessor interface signals ...................................................................... A-5
JTAG and TAP controller signals ................................................................. A-6
Debug signals............................................................................................... A-8
Miscellaneous signals................................................................................. A-10
ARM DDI 0180A