RM9200 Atmel Corporation, RM9200 Datasheet - Page 23

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.2
ARM DDI 0180A
Instruction interface
The 1,1 case does not occur in this implementation but may be used in the future.
Whenever an instruction enters the execute stage of the pipeline, a new opcode is
fetched from the instruction bus. The ARM9TDMI processor core may be connected to
a variety of cache/SRAM systems, and it is optimized for single cycle access systems.
However, in order to ease the system design, it is possible to connect the ARM9TDMI
to memory which takes two (or more) cycles for a non-sequential (N) access, and one
cycle for a sequential (S) access. Although this increases the effective CPI, it
considerably eases the memory design.
The ARM9TDMI indicates that an instruction fetch will take place by driving
InMREQ LOW. The instruction address bus, IA[31:1] will contain the address for the
fetch, and the ISEQ signal will indicate whether the fetch is sequential or
non-sequential to the previous access. All these signals become valid towards the end
of phase 2 of the cycle that precedes the instruction fetch.
If ITBIT is LOW, and thus ARM9TDMI is performing word reads, then IA[1] should
be ignored.
The timing is shown in Figure 3-2 on page 3-6. The full encoding of InMREQ and
ISEQ is as follows:
Instruction fetches may be marked as aborted. The IABORT signal is an input to the
processor with the same timing as the instruction data. If, and when, the instruction
reaches the execute stage of the pipeline, the prefetch abort vector is taken. The timing
for this is shown in Figure 3-2 on page 3-6. If the memory control logic does not make
use of the IABORT signal, it must be tied LOW.
Note
© Copyright ARM Limited 2000. All rights reserved.
InMREQ
0
0
1
1
Table 3-1 InMREQ and ISEQ encoding
ISEQ
0
1
0
1
Cycle type
Non-sequential
Sequential
Internal
Reserved for future use
3-5