RM9200 Atmel Corporation, RM9200 Datasheet - Page 63

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.5.1
5.5.2
5.5.3
ARM DDI 0180A
Reset
Pullup resistors
Instruction register
A clock on TCK is not needed to reset the device.
The JTAG interface includes a state-machine controller (the TAP controller). In order
to force the TAP controller into the correct state after power-up of the device, a reset
pulse must be applied to the nTRST signal. If the JTAG interface is to be used, nTRST
must be driven LOW, and then HIGH again. If the boundary scan interface is not to be
used, the nTRST input may be tied permanently LOW.
The action of reset is as follows:
1.
2.
The IEEE 1149.1 standard effectively requires TDI and TMS to have internal pullup
resistors. In order to minimize static current draw, these resistors are not fitted to the
ARM9TDMI. Accordingly, the four inputs to the test interface (the TDO, TDI and
TMS signals plus TCK) must all be driven to valid logic levels to achieve normal
circuit operation.
The instruction register is four bits in length. There is no parity bit. The fixed value
loaded into the instruction register during the CAPTURE-IR controller state is 0001.
System mode is selected. The boundary scan chain cells do not intercept any of
the signals passing between the external system and the core.
The IDCODE instruction is selected. If the TAP controller is put into the
Shift-DR state and TCK is pulsed, the contents of the ID register are clocked out
of TDO.
Note
© Copyright ARM Limited 2000. All rights reserved.
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