RM9200 Atmel Corporation, RM9200 Datasheet - Page 79

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.10 Determining the core state and system state
5.10.1
ARM DDI 0180A
Determining the core state
When the ARM9TDMI is in debug state, the core state and system state may be
examined. This is done by forcing load and store multiples into the pipeline.
Before the core state and system state can be examined, the debugger must first
determine whether the processor was in Thumb or ARM state when it entered debug.
This is achieved by examining bit 4 of the EmbeddedICE macrocell debug status
register. If this is HIGH, the core was in Thumb state when it entered debug. If it is
LOW, the core is in ARM state.
If the processor has entered debug state from Thumb state, the simplest course of action
is for the debugger to force the core back into ARM state. Once this is done, the
debugger can always execute the same sequence of instructions to determine the
processor state.
To force the processor into ARM state, the following sequence of Thumb instructions
should be executed on the core:
STR R0, [R1]; Save R0 before use
MOV R0, PC; Copy PC into R0
STR R0, [R1]; Save the PC in R0
BX PC; Jump into ARM state
MOV R8, R8; NOP (no operation)
MOV R8, R8; NOP
The above use of R1 as the base register for the stores is for illustration only—any
register could be used.
Since all Thumb instructions are only 16 bits long, the simplest course of action when
shifting them into scan chain 1 is to repeat the instruction twice on the instruction data
bus bits. For example, the encoding for
into the 32 bits of the instruction data bus of scan chain 1, the debugger does not have
to track from which half of the bus the processor expects to read instructions.
From this point on, the processor state can be determined by the sequences of ARM
instructions described below.
Once the processor is in ARM state, typically the first instruction executed would be:
STM R0, {R0-R15}
This causes the contents of the registers to be made visible on the data data bus. These
values can then be sampled and shifted out.
© Copyright ARM Limited 2000. All rights reserved.
BX R0
is 0x4700. Thus, if 0x47004700 is shifted
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