RM9200 Atmel Corporation, RM9200 Datasheet - Page 39

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0180A
GO
LAST
For both MRC and STC instructions, the DDIN[31:0] bus is owned by the coprocessor,
and can hence be driven by the coprocessor from the cycle after the relevant instruction
enters the execute stage of the coprocessor pipeline, until the next instruction enters the
execute stage of the coprocessor pipeline. This is the case even if the instruction is
subject to a LATECANCEL or the PASS signal is not asserted.
For efficient coprocessor design, an unmodified version of GCLK should be applied to
the execution stage of the coprocessor. This will allow the coprocessor to continue
executing an instruction even when the ARM9TDMI pipeline is stalled.
© Copyright ARM Limited 2000. All rights reserved.
coprocessor must not commit to the instruction (it must not change any
of the coprocessor’s state) until it has seen PASS HIGH, when the
handshake signals indicate the GO or LAST condition.
The GO state indicates that the coprocessor can execute the instruction
immediately, and that it requires another cycle of execution. Both the
ARM9TDMI processor core and the coprocessor must also consider the
state of the PASS signal before actually committing to the instruction.
For an LDC or STC instruction, the coprocessor instruction drives the
handshake signals with GO when two or more words still need to be
transferred. When only one further word is to be transferred, the
coprocessor drives the handshake signals with LAST.
In phase 2 of the execute stage, the ARM9TDMI processor core outputs
the address for the LDC/STC. Also in this phase, DnMREQ is driven
LOW, indicating to the memory system that a memory access is required
at the data end of the device. The timing for the data on DD[31:0] for an
LDC and DD[31:0] for an STC is shown in Figure 4-1 on page 4-4.
An LDC or STC can be used for more than one item of data. If this is the
case, possibly after busy waiting, the coprocessor drives the coprocessor
handshake signals with a number of GO states, and in the penultimate
cycle LAST (LAST indicating that the next transfer is the final one). If
there was only one transfer, the sequence would be
[WAIT,[WAIT,...]],LAST.
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