SAM3S2B Atmel Corporation, SAM3S2B Datasheet - Page 649
SAM3S2B
Manufacturer Part Number
SAM3S2B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2B
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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31.11.6
Name:
Addresses: 0x40018020 (0), 0x4001C020 (1)
Access:
Reset:
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 640
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 640
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
6500C–ATARM–8-Feb-11
TXBUFE
31
23
15
–
–
7
–
and
and
TWI Status Register
TWI_SR
Read-only
0x0000F009
Figure 31-31 on page
Figure 31-31 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
640.
640.
29
21
13
–
–
5
Figure 31-8 on page
Figure 31-10 on page
Figure 31-26 on page
ENDRX
SVACC
Figure 31-28 on page
Figure 31-8 on page 621
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
621.
622.
636,
638,
and in
Figure 31-29 on page
Figure 31-29 on page
SCLWS
TXRDY
26
18
10
–
–
2
Figure 31-10 on page
ARBLST
RXRDY
25
17
–
–
9
1
639,
639,
622.
Figure 31-30 on
Figure 31-30 on
SAM3S
TXCOMP
NACK
24
16
–
–
8
0
649
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