SAM3S2B Atmel Corporation, SAM3S2B Datasheet - Page 989
SAM3S2B
Manufacturer Part Number
SAM3S2B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2B
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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39.6.11
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
PDC Buffer Structure
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value
between two channel selections. This time has to be programmed through the TRACKTIM bit
field in the Mode Register, ADC_MR.
When the gain, offset or differential input parameters of the analog cell change between two
channels, the analog cell may need a specific settling time before starting the tracking phase. In
that case, the controller automatically waits during the settling time defined in the
Register”. Obviously, if the ANACH option is not set, this time is unused.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be
taken into consideration to program a precise value in the TRACKTIM field. See the product
ADC Characteristics section.
The PDC read channel is triggered each time a new data is stored in ADC_LCDR register. The
same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event
occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2) the structure differs. Each data transferred to PDC buffer, carried on a half-word
(16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register,
the 4 most significant bits are carrying the channel number thus allowing an easier post-process-
ing in the PDC buffer or better checking the PDC buffer integrity.
SAM3S
SAM3S
“ADC Mode
989
989
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