SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 37
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
10.11 LCD Controller (LCDC)
10.12 Ethernet 10/100 MAC (EMAC)
11053AS–ATARM–27-Jul-11
• One Master
• Up to 266MHz input clock
• 384-byte Asynchronous Output FIFO
• One Background Layer
• One High End Overlay Layer, YUV Full planar, 4.2.0, 4.2.2 packed
• One Overlay RGB
• One Hardware cursor with user-defined size
• Up to 24 bits per Pixel in TFT Mode
• Dithering for 12bpp, 16bpp and 18bpp modes
• LUT for 1bpp, 2bpp, 4bpp and 8bpp
• Resolution Up to 2048x2048 pixels
• Supported formats:
• alpha blending, color conversion, rotation
• scaling up to 800x600 pixels
• supports RMII Mode only
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operations
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
• Support Wake On Lan: The receiver supports Wake on LAN by detecting the following events
on incoming receive frames:
– RGB: 444 (12bpp), 565 (16bpp), 666 (18bpp), 888 (24bpp and packed 24bpp)
– Transparency + RGB: 1555 (16bpp), 1666 (19bpp and packed 19bpp), 1888 (25bpp)
– Alpha + RGB or RGB + Alpha: 4444 (16bpp), 8888 (32bpp)
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match
SAM9G35
37