SAM9M11 Atmel Corporation, SAM9M11 Datasheet
SAM9M11
Specifications of SAM9M11
Related parts for SAM9M11
SAM9M11 Summary of contents
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... Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91SAM ARM-based Embedded MPU SAM9M11 Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. 6437CS–ATARM–8-Apr-11 ...
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... USB and SDIO. The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263 (720 x 576 pixels) or WVGA (800 x 480) resolutions at 30 frames per second (fps). The SAM9M11 also provides hardware image post-processing, such as image scaling, color conversion and image rotation ...
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... Block Diagram Figure 2-1. SAM9M11 Block Diagram 6437CS–ATARM–8-Apr-11 PIO SAM9M11 3 ...
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... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output SAM9M11 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
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... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O SAM9M11 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
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... NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read SAM9M11 6 Active Type Level I/O I/O I/O DDR Memory Interface - DDR2/LPDDR Controller I/O Output Output Output High Output ...
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... Output Low Output Output Output High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O SAM9M11 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 (1) (1) ...
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... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + SAM9M11 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
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... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog SAM9M11 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. SAM9M11 10 Active Reference ...
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... Package and Pinout The SAM9M11 is delivered in a 324-ball LFBGA package. 4.1 Mechanical Overview of the 324-ball LFBGA Package Figure 4-1 Figure 4-1. 6437CS–ATARM–8-Apr-11 shows the orientation of the 324-ball LFBGA Package Orientation of the 324-ball LFBGA Package ...
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... TFBGA Package Pinout Table 4-1. SAM9M11 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS F3 A13 SDCK ...
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... Table 4-1. SAM9M11 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 H17 ...
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... Power Considerations 5.1 Power Supplies The SAM9M11 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface 6437CS–ATARM–8-Apr-11 ® ® technology for Java acceleration each quarter of the page system flexibility 32-bit data interface (Words) SAM9M11 15 ...
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... Allows Handling of Dynamic Exception Vectors 6.2.1 Matrix Masters The Bus Matrix of the SAM9M11 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... UDP High Speed RAM LCD User Interface Video Decoder DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 External Bus Interface Internal Peripherals Video Decoder is not enabled (VDEC_SEL=0) Video Decoder is enabled (VDEC_SEL=1), SAM9M11 , the ARM instruction and data are DDR Port 0 is dedicated to the video 17 ...
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... DDR Port DDR Port DDR Port EBI X 7 Internal Periph. X SAM9M11 18 Video Mode Configuration Video Decoder LCD + Post Processing DMA MATRIX SAM9M11 Masters to Slaves Access with VDEC_SEL = & 5 USB Host PDC OHCI DMA ...
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... Acting as one AHB Bus Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer support, prevents strong real-time constraints on buffer management. 6437CS–ATARM–8-Apr-11 SAM9M11 Masters to Slaves Access with VDEC_SEL = 1 (default & 5 ...
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... SSC1 SSC0 6.4 USB The SAM9M11 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port ...
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... SSC1 AC97 AC97 MCI1 6437CS–ATARM–8-Apr-11 USB Selection HS HS Transceiver Transceiver EHCI FS OHCI DMA DMA Channel Definition DMA Channel HW T/R interface Number TX/ TX/RX 13 SAM9M11 EN_UDPHS 1 HS USB DMA 21 ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. SAM9M11 22 6437CS–ATARM–8-Apr-11 ...
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... Memories Figure 7-1. SAM9M11 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 256M Bytes 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ 256M Bytes DDRSDRC1 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Internal SRAM The SAM9M11 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is per- formed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After Remap, the SRAM also becomes available at address 0x0 ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The SAM9M11 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
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... Switch the main clock to the new value 7.3 External Memories The SAM9M11 features a Multi-port DDR2 Interface and an External Bus Interface allowing to connect to a wide range of external memories and to any parallel peripheral. 7.3.1 DDRSDRC0 Multi-port DDRSDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini- mizes Transaction Latency. • ...
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... Asynchronous read in Page Mode supported ( 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation 6437CS–ATARM–8-Apr-11 Average Latency of Transactions) SAM9M11 TM M support 27 ...
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... Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 8. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. SAM9M11 28 Average Latency of Transactions) detected erroneous pages 6437CS– ...
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... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 30 Figure 7-1 on page 23 peripherals. 6437CS–ATARM–8-Apr-11 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller SAM9M11 29 ...
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... System Controller Block Diagram Figure 8-1. SAM9M11 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC ...
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... MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro. 6437CS–ATARM–8-Apr-11 SAM9M11 31 ...
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... Figure 8-2. 8.6 Slow Clock Selection The SAM9M11 slow clock can be generated either by an external 32768Hz crystal or the on- chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec- tively RCEN bit and OSC32EN bit in the system controller user interface ...
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... Enable the internal RC oscillator by setting the bit RCEN to 1. • Wait internal RC Startup Time for clock stabilization (software loop). 6437CS–ATARM–8-Apr-11 Slow Clock Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9M11 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 33 ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery SAM9M11 34 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
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... Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) • System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz • MDIV is ‘01’, MCK is 120 MHz • Only LP-DDR can be used 120 MHz 6437CS–ATARM–8-Apr-11 SAM9M11 Power Management Controller Block Diagram USBS USBDIV+1 /1,/2 UPLLCK Prescaler /1,/2,/4, ...
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... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive SAM9M11 36 Controller 6437CS–ATARM–8-Apr-11 ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 8.15 Chip Identification The SAM9M11 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A1 • Ext ID: 0x00000001 • ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write SAM9M11 38 6437CS–ATARM–8-Apr-11 ...
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... UDPHS 28 AES, TDES, SHA 6437CS–ATARM–8-Apr-11 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9M11. A peripheral identifier is required Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.4 Peripheral Signals Multiplexing on I/O Lines The SAM9M11 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi- plexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... ETX3 I/O VDDIOP0 ERX2 I/O VDDIOP0 ERX3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 SCK3 I/O VDDIOP0 RTS3 I/O VDDIOP0 CTS3 I/O VDDIOP0 PWM3 I/O VDDIOP0 TIOB2 I/O VDDIOP0 ETXER I/O VDDIOP0 ERXCK I/O VDDIOP0 ECRS I/O VDDIOP0 ECOL I/O VDDIOP0 PCK0 I/O VDDIOP0 SAM9M11 Function Comments 41 ...
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... TXD0 PB20 ISI_D0 PB21 ISI_D1 PB22 ISI_D2 PB23 ISI_D3 PB24 ISI_D4 PB25 ISI_D5 PB26 ISI_D6 PB27 ISI_D7 PB28 ISI_PCK PB29 ISI_VSYNC PB30 ISI_HSYNC PB31 ISI_MCK SAM9M11 42 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ISI_D8 I/O VDDIOP2 ...
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... A20 VDDIOM1 A21 VDDIOM1 A22 VDDIOM1 A23 VDDIOM1 A24 VDDIOM1 I/O VDDIOM1 RTS2 I/O VDDIOM1 TCLK2 I/O VDDIOM1 CTS2 I/O VDDIOM1 A25 VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 SAM9M11 Function Comments 43 ...
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... SPI1_NPCS3 PD20 TIOA0 PD21 TIOA1 PD22 TIOA2 PD23 TCLK0 PD24 SPI0_NPCS1 PD25 SPI0_NPCS2 PD26 PCK0 PD27 PCK1 PD28 TSADTRG PD29 TCLK1 TIOB0 PD30 PD31 TIOB1 SAM9M11 44 Reset Power Peripheral B State Supply PWM3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 TIOA5 I/O VDDIOP0 ...
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... LCDD5 I/O VDDIOP1 LCDD6 I/O VDDIOP1 LCDD7 I/O VDDIOP1 LCDD10 I/O VDDIOP1 LCDD11 I/O VDDIOP1 LCDD12 I/O VDDIOP1 LCDD13 I/O VDDIOP1 LCDD14 I/O VDDIOP1 LCDD15 I/O VDDIOP1 LCDD18 I/O VDDIOP1 LCDD19 I/O VDDIOP1 LCDD20 I/O VDDIOP1 LCDD21 I/O VDDIOP1 LCDD22 I/O VDDIOP1 LCDD23 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 PCK1 I/O VDDIOP1 SAM9M11 Function Comments 45 ...
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... Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS SAM9M11 46 peripherals Sensors and data per chip select 6437CS–ATARM–8-Apr-11 ...
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... Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 6437CS–ATARM–8-Apr-11 SAM9M11 2 S, TDM Buses, Magnetic Card Reader,...) 47 ...
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... Independent Period and Duty Cycle, with Double Buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.8 High Speed Multimedia Card Interface (MCI) • Compatibility with MultiMedia Card Specification Version 4.3 SAM9M11 48 6437CS–ATARM–8-Apr-11 ...
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... STN • bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048 x 2048 6437CS–ATARM–8-Apr-11 SAM9M11 49 ...
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... ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats SAM9M11 50 enabled channels 6437CS–ATARM–8-Apr-11 ...
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... Writing a stream of data into non-contiguous fields in system memory transfer programmed values at the end of a block transfer of block transfer in block chaining mode to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition SAM9M11 51 ...
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... One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support 10.19 Secure Hash Algorithm (SHA) • Supports Secure Hash Algorithm (SHA1 and SHA256) • Compliant with FIPS Publication 180-2 • Configurable Processing Period: SAM9M11 52 6437CS–ATARM–8-Apr-11 ...
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... Alpha blending • De-blocking filter for MPEG-4 simple profile/H.263 • Image cropping / digital zoom • Picture in picture • Supported display size for picture in picture • Image rotation 6437CS–ATARM–8-Apr-11 Applications in PDC (Peripheral DMA) Other Applications in PDC (Peripheral DMA) SAM9M11 53 ...
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... Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing SAM9M11 54 6437CS–ATARM–8-Apr-11 ...
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... SAM9M11 Ordering Information Table 12-1. AT91SAM9M11 Ordering Information Ordering Code AT91SAM9M11-CU 6437CS–ATARM–8-Apr-11 Package Package Type TFBGA324 Green SAM9M11 Temperature Operating Range Industrial -40°C to 85°C 55 ...
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... Revision History Doc. Rev Comments Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9M11 Section 5.1 “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, 6355CS GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins Section 10.20 “Video Decoder (VDEC)” ...
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