SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 34
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SAM9M11
Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Specifications of SAM9M11
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
8.7
34
Power Management Controller
SAM9M11
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
PMC output clocks
Note:
This allows the software control of five flexible operating modes:
• Switch from 32768 Hz oscillator to internal RC oscillator by setting the bit OSCSEL to 0.
• Wait 5 slow clock cycles for internal resynchronization.
• Disable the 32768Hz oscillator by setting the bit OSC32EN to 0.
• UPLLCK: From UTMI PLL
• PLLACK From PLLA
• SLCK: slow clock from OSC32K or internal RC OSC
• MAINCK: from 12 MHz external oscillator
• Processor Clock PCK
• Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be
• DDR system clock equal to 2xMCK
• USB Host EHCI High speed clock (UPLLCK)
• USB OHCI clocks (UHP48M and UHP12M)
• Independent peripheral clocks, typically at the frequency of MCK
• Two programmable clock outputs: PCK0 and PCK1
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
1,2,3 or 4
stopped waiting for an interrupt
DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
6437CS–ATARM–8-Apr-11