SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 51
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SAM9M11
Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Specifications of SAM9M11
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
10.15 8-channel DMA (DMA)
10.16 True Random Number Generator (TRNG)
10.17 Advanced Encryption Standard (AES)
6437CS–ATARM–8-Apr-11
• Preview scaler to generate smaller size image
• Acting as two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
• Channel Control
• Transfer Initiation
• Interrupt
• Passed NIST Special Publication 800-22 Tests Suite
• Passed Diehard Random Tests Suite
• Provides a 32-bit Random Number Every 84 Clock Cycles
• For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s
• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
– Source/Destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
– 16-word FIFO
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
– Support for Software handshaking interface. Memory mapped registers can be used
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
SAM9M11
51