SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 19

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.4
6254CS–ATARM–08-Jan-10
Debug and Test Features
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
• ARM926 Real-time In-circuit Emulator
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
– TWI0 Transmit Channel
– TWI1 Transmit Channel
– DBGU Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC Transmit Channel
– TWI0 Receive Channel
– TWI1 Receive Channel
– DBGU Receive Channel
– USART4 Receive Channel
– USART3 Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– ADC Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC Receive Channel
– MCI Transmit/Receive Channel
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
AT91SAM9XE128/256/512 Preliminary
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