SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 46

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

13. Revision History
46
Doc Rev.
6254CS
Doc. Rev
6254BS
6254AS
AT91SAM9XE128/256/512 Preliminary
Comments
Removed 6.8, Slow CLock Selection (is shown in 27.5 of the full datasheet)
Removed fomer Section 5.2 “Power Consumption”.
Removed Clock Generator block diagram from
full datasheet).
Removed PMC block diagram from
the full datasheet).
“Features”,
“Ethernet MAC 10/100
Debug Unit (DBGU), added, Mode for general purpose6-2-wire UART serial communication
Section 9.13 “Chip
Table 3-1, “Signal Description
PIOA - PIOB - PIOC” , has a foot note added to its comments column. SHDWN is active Low.
Section 5.1 “Power
Section 6. “I/O Line
“Features”,
“Features”,
Manchester Encoding/Decoding.
Section 6.3 “Shutdown Logic
First issue.
Comments
Table 3-1, “Signal Description
removed. Cross reference referring to PIO Multiplexing added to these signals.
Table 10-3, “Multiplexing on PIO Controller
Table 10-4, “Multiplexing on PIO Controller
Section 8-1 “AT91SAM9XE128/256/512 Memory
Section 6.1 “ERASE
Section 7.2.2 “Matrix Slaves”
Slave order changed in
Section 8.1.4 “ROM
Section 8.1.4.1 “Fast Flash Programming
Table 3-1, “Signal Description List,”
Section 9.2 “Reset
Section 8.2.5 “I/O Drive
GLobal: KB rewritten as -Kbyte or Kbytes, MB as Mbytes or -Mbyte (conform to style guide; lit° 3363B)
“Additional Embedded
“Four Universal Synchronous/Asynchronous Receiver Transmitters
Identification”, SAM9XE512 chip ID is 0x329AA3A0.
Controller”, added: “At reset the NRST pin is an output”.
Supplies”, added “Caution: VDDCORE and VDDIO constraints.......
Considerations”, unneeded paragraphs removed.
Topology”and
Pin”, ERASE pin is powered by VDDIOP0 rail.
Base-T”, 128-byte FIFOs (typo corrected).
Table 7-2
Selection”, added to datasheet.
Pins”, updated with external pull-up requirement.
and
List”, PCKx, DBGU, AIC, PIOC, USART, SSC, TC, SPI, TWI voltage references
List,””, comment column updated in certain instances and “PIO Controller -
Section 7.2.3 “Masters to Slaves Access”
and
Memories”Fast Read Time: 45 ns
Figure 8-2 “ROM Boot Memory
Section 9.6 “Power Management Controller”
PGMEN[3:0] replaces PGMEN[2:0].
Table 7-3
Interface”, added PA3.
B”, PB16 to PB21, Peripheral A column updated.
C”, PC0 to PC3, Power Supply column updated.
Section 9.5 “Clock Generator”
Mapping”, GPBR addresses changed.
Table
Map”, added PA3.
8-1, added PGMEN3 and PA3.
(is shown in Figure 27.1 of the
(USART)”, added
(is shown in Figure 28.1 of
6254CS–ATARM–08-Jan-10
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Request
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