SAM3N0B Atmel Corporation, SAM3N0B Datasheet - Page 163

• Manufacturer Part Number: SAM3N0B
• Manufacturer: Atmel Corporation

10.20.10 NVIC design hints and tips
10.20.10.1
11011A–ATARM–04-Oct-10
NVIC programming hints
Ensure software uses correctly aligned register accesses. The processor does not support
unaligned accesses to NVIC registers. See the individual register descriptions for the supported
access sizes.
A interrupt can enter pending state even it is disabled.
Before programming VTOR to relocate the vector table, ensure the vector table entries of the
new vector table are setup for fault handlers and all enabled exception like interrupts. For more
information see
Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The
CMSIS provides the following intrinsic functions for these instructions:
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 10-29. CMSIS functions for NVIC control
For more information about these functions see the CMSIS documentation.
CMSIS interrupt control function
void NVIC_SetPriorityGrouping(uint32_t
priority_grouping)
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
uint32_t NVIC_GetActive (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
“Vector Table Offset Register” on page
Return true if IRQn is pending
Set priority for IRQn
Read priority of IRQn
Description
Set the priority grouping
Enable IRQn
Disable IRQn
Set IRQn pending
Clear IRQn pending status
Return the IRQ number of the active
interrupt
Reset the system
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