SAM3N0B Atmel Corporation, SAM3N0B Datasheet - Page 400
SAM3N0B
Manufacturer Part Number
SAM3N0B
Description
Manufacturer
Atmel Corporation
- Current page: 400 of 752
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Table 26-2.
Notes:
Note:
400
400
Offset
0x0104-
0x010C
0x0110
0x0114-
0x011C
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
if an offset is not listed in the table it must be considered as reserved.
SAM3N
SAM3N
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
occurred.
Register
Reserved
Reserved
Reserved
Register Mapping (Continued)
Name
–
–
–
Access
–
–
–
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Reset
–
–
–
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